LMU112
DEVICES INCORPORATED
12 x 12-bit Parallel Multiplier
F
IGURE
1
A
.
I
NPUT
F
ORMATS
A
IN
Fractional Two’s Complement (TC = 1)
11 10 9
–2
0
2
–1
2
–2
(Sign)
B
IN
2 1 0
2
–9
2
–10
2
–11
11 10 9
–2
0
2
–1
2
–2
(Sign)
2 1 0
2
–9
2
–10
2
–11
Integer Two’s Complement (TC = 1)
11 10 9
–2
11
2
10
2
9
(Sign)
2 1 0
2
2
2
1
2
0
11 10 9
–2
11
2
10
2
9
(Sign)
2 1 0
2
2
2
1
2
0
Unsigned Fractional (TC = 0)
11 10 9
2
–1
2
–2
2
–3
2 1 0
2
–10
2
–11
2
–12
11 10 9
2
–1
2
–2
2
–3
2 1 0
2
–10
2
–11
2
–12
Unsigned Integer (TC = 0)
11 10 9
2
11
2
10
2
9
2 1 0
2
2
2
1
2
0
11 10 9
2
11
2
10
2
9
2 1 0
2
2
2
1
2
0
F
IGURE
1
B
.
O
UTPUT
F
ORMATS
MSP
Fractional Two’s Complement
23 22 21
–2
0
2
–1
2
–2
(Sign)
LSP
14 13 12
2
–9
2
–10
2
–11
Integer Two’s Complement
11 10 9 8
2
–12
2
–13
2
–14
2
–15
23 22 21
–2
22
2
21
2
20
(Sign)
14 13 12
2
13
2
12
2
11
Unsigned Fractional
11 10 9 8
2
10
2
9
2
8
2
7
23 22 21
2
–1
2
–2
2
–3
14 13 12
2
–10
2
–11
2
–12
Unsigned Integer
11 10 9 8
2
–13
2
–14
2
–15
2
–16
23 22 21
2
23
2
22
2
21
14 13 12
2
14
2
13
2
12
11 10 9 8
2
11
2
10
2
9
2
8
Multipliers
2
08/16/2000–LDS.112-K
LOGIC [ LOGIC DEVICES INCORPORATED ]
