LMS12
DEVICES INCORPORATED
12-bit Cascadable Multiplier-Summer
F
IGURE
1.
F
LOW
D
IAGRAM FOR
5-T
AP
FIR F
ILTER
x(n)
h
4
h
3
h
2
h
1
h
0
Z
–1
Z
–1
Z
–1
Z
–1
y(n)
x(n)
A
4
A
3
A
2
A
1
A
0
h
4
h
3
h
2
h1
h
0
Z
–1
Z
–1
Z
–1
Z
–1
Z
–1
y(n)
APPLICATIONS
The LMS12 is designed specifically for
high-speed FIR filtering applications
requiring a throughput rate of one
output sample per clock period. By
cascading LMS12 units, the transpose
form of the FIR transfer function is
implemented directly, with each of the
LMS12 units supplying one of the
filter weights, and the cascaded
summers accumulating the results.
The signal flow graph for a 5-tap FIR
filter and the equivalent implementa-
tion using LMS12’s is shown in
Figure 1.
The operation of the 5-tap FIR filter
implementation of Figure 1 is depicted
in Table 1. The filter weights h
4
- h
0
are assumed to be latched in the B
input registers of the LMS12 units.
The x(n) data is applied in parallel to
the A input registers of all devices.
For descriptive purposes in the table,
the A register contents and sum
output data of each device is labelled
according to the index of the weight
applied by that device; i.e., S
0
is
produced by the rightmost device,
which has h
0
as its filter weight and
A
0
as its input register contents. Each
column represents one clock cycle,
with the data passing a particular
point in the system illustrated across
each row.
Multiplier-Summers
2
08/16/2000–LDS.S12-J
LOGIC [ LOGIC DEVICES INCORPORATED ]
