LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
F
IGURE
4.
LF48908 C
ONTROL
L
OGIC
B
LOCK
D
IAGRAM
ENCR
1
3
A
2-0
LD
CS
ADDRESS
DECODE
ENCR
0
CAS
CR
1
CR
0
LMC
EOR
1
2
10
ALU MICROCODE
10
CIN
9-0
LMC
ALU MICROCODE REGISTER
3
10
EOR
9
INITIALIZATION REGISTER
ROW LENGTH REGISTER
ROW LENGTH
8-0
CAS
9
INITIALIZATION DATA
4
5
C
0
OE
OE
COEFFICIENT REGISTER 0
7-0
CR
0
8
I
0
OE
H
0
OE
G
0
OE
F
0
OE
E
0
OE
D
0
B
0
OE
A
0
OE
8
I
ENCR
1
ENCR
0
S Q
R Q
8
8
H
8
G
8
8
8
8
8
6
7
A
OE
F
E
D
C
B
7-0
CR
1
8
OE
OE
OE
OE
OE
OE
OE
OE
8
9
I
1
H
1
G
1
F
1
E
1
D
1
C
1
B
1
A
1
COEFFICIENT REGISTER 1
through the CIN bus using A
2-0
, CS,
and LD (see Figure 4). All the Control
Logic Registers are set to their default
values when RESET is active. FRAME
does not affect the values in these
registers.
ALU Microcode Register
Operation of the ALU and shifter are
determined by the value stored in the
ALU Microcode Register. This 10-bit
instruction word is divided into two
fields. The lower seven bits define the
arithmetic and logical operations of the
ALU. The upper three bits specify shift
distance and direction. Tables 1 and 2
detail the various instruction words.
This register is loaded through CIN
9-0
using the A
2-0
, CS, and LD controls.
Also see Arithmetic Logic Unit section.
Row Length Register
The value stored in the Row Length
Register determines the number of
delay stages for each row buffer. The
number of delay stages should be set
equal to the row length of the input
image. The Row Length Register may
be loaded with the values 0 through
1023 (0 represents 1024 delay stages).
It is possible to program the row
buffers to have 1 or 2 delay stages, but
this will lead to meaningless results
for a 3 x 3 convolution. This register is
loaded through CIN
9-0
using the A
2-0
,
CS, and LD controls. Once the Row
Length Register has been loaded, a
new value can not be loaded until the
LF48908 has been reset. This is done
by asserting RESET. After RESET goes
HIGH, the Row Length Register must
be loaded within 1024 CLK cycles. If
the Row Length Register is not loaded
within 1024 CLK cycles, the register
will automatically be loaded with a “0”.
Initialization Register
The Initialization Register configures
various functions of the device
including: input data delay, input
data format, coefficent data format,
output rounding, cascade mode, and
cascade input shift (see Table 3). This
register is loaded through CIN
8-0
using the A
2-0
, CS, and LD controls.
Coefficient Registers - CREG
0
, CREG
1
The Coefficient Registers are used to
store the filter coefficients for the
multiplier array. Each Coefficient
10
11
Video Imaging Products
5
08/9/2000–LDS.48908-J
LOGIC [ LOGIC DEVICES INCORPORATED ]
