LF48908
DEVICES INCORPORATED
Two Dimensional Convolver
T
ABLE
3. I
NITIALIZATION
R
EGISTER
BIT
0
0
FUNCTION
CASCADE MODE
Multiplier input from internal row buffers
Multiplier input from external buffers
1
0
1
0
1
3
0
1
4
0
1
6
0
0
1
1
8
0
0
1
1
5
0
1
0
1
7
0
1
0
1
INPUT DATA DELAY
No data delay registers used
One data delay register used
Two data delay registers used
Three data delay registers used
INPUT DATA FORMAT
Unsigned integer format
Two’s complement format
COEFFICIENT DATA FORMAT
Unsigned integer format
Two’s complement format
OUTPUT ROUNDING
No rounding
Round to 16 bits (i.e. DOUT19-4)
Round to 8 bits (i.e. DOUT19-12)
Not valid
CASI15-0 INPUT SHIFT
No shift
Shift CASI15-0 left two
Shift CASI15-0 left four
Shift CASI15-0 left eight
be ignored. If the LF48908 is not in
active operation or if the innactive
Coefficient Register is being written to
during active operation.
Cascade Operation
The Cascade Input lines (CASI
15-0
)
and Cascade Output lines (CASO
7-0
)
are used to allow convolutions of
kernel sizes larger than 3 x 3. The
Cascade Input lines are also used to
allow convolutions on row lengths
longer than 1024 pixels. The Cascade
Mode Bit (Bit 0) of the Initialization
Register determines the function of
the Cascade Input lines. If the Cas-
cade Mode Bit is a “0”, then the
Cascade Input lines are to be used to
cascade multiple LF48908s together to
perform convolutions of larger kernel
sizes. CASI
15-0
will be left shifted (by
an amount determined by bits 7 and 8
of the Initialization Register) and then
added to DOUT
19-0
. Cascading is
accomplished by connecting CASO
7-0
and DOUT
19-0
of one LF48908 to
DIN
7-0
and CASI
15-0
respectively of
another LF48908. If the Cascade
Mode Bit is a “1”, then the Cascade
Input lines are to be used with exter-
nal row buffers to allow for longer
row lengths. In this mode, the Cas-
cade Input lines are split into two 8-bit
data busses (CASI
15-8
and CASI
7-0
)
which are fed directly into the multi-
plier array.
T
ABLE
4.
A
2-0
000
001
010
011
100
101
110
111
C
ONTROL
L
OGIC
A
DDRESS
M
AP
FUNCTION
1
2
0
0
1
1
Load Row Buffer Length
Register
Load ALU Microcode Register
Load Coefficient Register 0
Load Coefficient Register 1
Load Initialization Register
Select Coefficient Register 0
for Internal Processing
Select Coefficient Register 1
for Internal Processing
No Operation
1
2
3
4
5
6
7
8
9
10
11
Video Imaging Products
7
08/9/2000–LDS.48908-J
LOGIC [ LOGIC DEVICES INCORPORATED ]
