LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
DIO23-0 (if RD is LOW). If Look Up
Table Write Mode was used to load
the memory array, it is important to
wait until the third clock cycle after
START goes HIGH to input data on
PIN9-0 to insure that all data is
FIGURE 3. LOOK UP TABLE MODE
RAM ARRAY
DATA IN DATA OUT
ADDRESS WR
24
DIN23-0
written into the memory array before
any reading is done.
24
DIO
I/F
DIO23-0
10
ADDRESS
PIN9-0
CLK
GENERATOR
COUNTER
CONTROL
"0"
BIN ACCUMULATE MODE
RD
When the LF48410 is in this mode, the
chip is configured as shown in Figure
4. PIN9-0 provides address data for
(TO ALL REGISTERS)
START
NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPELINE DELAYS.
the memory array and is latched on
the rising edge of CLK. Data at the
address defined by PIN9-0 is read out
of the memory array and added to
the data on DIN23-0. This new value
is written back to the memory array,
in the same location where the last
read occured, and is also output on
DIO23-0 (if RD is LOW). As long as
START is LOW, the device will be
enabled for Bin Accumulate Mode.
When START is HIGH, the device will
still read address values on PIN9-0, but
the addressed data will not be added
to anything. The unchanged data will
be output on DIO23-0 and is not
FIGURE 4. BIN ACCUMULATE MODE
RAM ARRAY
DATA IN
DATA OUT
ADDRESS WR
24
24
10
DIO
I/F
DIO23-0
DIN23-0
PIN9-0
ADDRESS
GENERATOR
RD
"0"
written back to the memory array
(writing is disabled). START and
DIN23-0 are delayed internally three
clock cycles to match the latency of
the address generator.
START
CLK
CONTROL
NOTE: NUMBER IN REGISTER INDICATES
NUMBER OF PIPELINE DELAYS.
TO ALL REGISTERS
into the memory array at the address
defined by the counter. The value
already in the memory array at that
sections. If the Cumulative Distribu-
tion Function is the desired transfor-
mation function, the memory array
DELAY MEMORY MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
5. This mode allows the device to
function as a row buffer. The internal
counter is used to generate address
data for the memory array. When
START goes LOW, the counter is
reset to zero. Delay length (row
length) is determined by reseting the
counter every N–4 clock cycles, where
N is the number of delays. For
address is output on DIO23-0 (if RD is will contain this data as soon as the
LOW). Every rising edge of CLK
causes the counter to increment its
output by one until the counter
Histogram Accumulate function has
been completed.
Once the memory array contains the
desired data, the device needs to be
put in Look Up Table Read Mode by
setting START HIGH. In Look Up
Table Read Mode, pixel values are
input on PIN9-0 and are latched on
the rising edge of CLK. Data at the
address defined by PIN9-0 is read out
of the memory array and output on
reaches a value of 1023. At this point,
the counter will hold the value of
1023 and writing to the memory array
will be disabled. DIN23-0 is delayed
internally three clock cycles to match
the latency of the address generator.
In Asynchronous 16/24 Mode, data is
loaded into the memory array as
detailed in the asynchronous mode
Video Imaging Products
08/08/2000–LDS.48410-L
4
LOGIC [ LOGIC DEVICES INCORPORATED ]
