LF48410
DEVICES INCORPORATED
1024 x 24-bit Video Histogrammer
F
IGURE
1.
H
ISTOGRAM
M
ODE
HISTOGRAM MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
1. The memory array keeps track of
how many times a particular pixel
value is used in a video image. The
pixel value is input on PIN
9-0
and is
latched on the rising edge of CLK.
Data at the address defined by PIN
9-0
is read out of the memory array and
incremented by one. The data is then
written back to the memory array, in
the same location it was read from,
and is also output on DIO
23-0
(if RD is
LOW). As long as START is LOW,
the device will be enabled for Histo-
gram Mode. When START is HIGH,
the device will still read pixel values,
but the addres-sed data will not be
incremented. The unchanged data is
output on DIO
23-0
and is not written
back to the memory array (writing is
disabled). START is delayed inter-
nally three clock cycles to match the
latency of the address generator.
HISTOGRAM ACCUMULATE
MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
2. This mode is used to calculate the
Cumulative Distribution Function of
a video image. Before this can be
done, the histogram of the image
must already be in the memory array.
The internal counter is used to
generate address data for the memory
array. Data at the address defined by
the counter is read out of the memory
array and added to the sum of the
data from all previous address
locations. This new value is written
back to the memory array, in the
same location where the last read
occurred, and is also output on
DIO
23-0
(if RD is LOW). After all
memory locations with histogram
data are accumulated, the memory
array will contain the Cumulative
Distribution Function.
After this mode is selected, the
internal counter and all data path
registers are reset to zero when
RAM ARRAY
DATA IN
DATA OUT
ADDRESS
WR
DIO
I/F
10
PIN
9-0
ADDRESS
GENERATOR
"0"
"1"
RD
24
DIO
23-0
START
CONTROL
CLK
TO ALL REGISTERS
F
IGURE
2.
H
ISTOGRAM
A
CCUMULATE
M
ODE
RAM ARRAY
DATA IN
DATA OUT
ADDRESS
WR
DIO
I/F
ADDRESS
GENERATOR
"0"
RD
CLK
(TO ALL REGISTERS)
COUNTER
24
DIO
23-0
START
CONTROL
START is set LOW. Every rising edge
of CLK causes the counter to incre-
ment its output by one until the
counter reaches a value of 1023. At
this point, the counter will hold the
value of 1023 and writing to the
memory array will be disabled. As
long as START is LOW, the device
will be enabled for Histogram Accu-
mulate Mode. When START is HIGH,
the counter will still increment its
address values, but the addressed
data will not be added to anything.
The unchanged data is output on
DIO
23-0
and is not written back to the
memory array (writing is disabled).
START is delayed internally three
clock cycles to match the latency of
the address generator.
LOOK UP TABLE MODE
When the LF48410 is in this mode, the
chip is configured as shown in Figure
3. This mode is used to perform fixed
transformation functions on pixel
values. The transformation function
can be loaded into the memory array
in Look Up Table Write Mode,
Asynchronous 16/24 Mode, or
Histogram Accumulate Mode. In
Look Up Table Write Mode, data is
loaded into the memory array using
DIN
23-0
, CLK, and START. The
internal counter is used to generate
address data for the memory array.
When START goes LOW, the counter
is reset to zero. As long as START is
LOW, data on DIN
23-0
is latched on
the rising edge of CLK and loaded
Video Imaging Products
3
08/08/2000–LDS.48410-L
LOGIC [ LOGIC DEVICES INCORPORATED ]
