LF43881
DEVICES INCORPORATED
8 x 8-bit Digital Filter
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
11. For the tENA test, the transition is
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
ation ofthese products at values beyond output reference levels of 1.5 V (except
those indicated in the Operating Condi-
with datasheet loads. For the tDIS test,
the transition is m easu red to the
tDIS test), and input levels of nominally
tions table is not implied. Exposure to 0 to 3.0 V. Output loading may be a ±200m V level from the m easured
maximum rating conditions for ex- resistive divider which provides for steady-state ou tp u t v oltage w ith
tended periods may affect reliability.
±10m A load s. The balancing volt-
age, VTH , is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
cumulations ofstaticcharge. Neverthe-
less, conventional precautions should
be observed during storage, handling,
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
stress values.
pulses and fast turn-on/ turn-off times.
As a result, care must be exercised in the
testing of this device. The following
measures are recommended:
S1
DUT
3. Thisdeviceprovideshard clamping of
transient undershoot and overshoot. In-
put levels below ground or above VCC
I
OL
VTH
CL
I
OH
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand installed between VCC and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
tion will not be adversely affected, how-
ever, input current levels will be well in and the tester common, and device
should be installed between device VCC
OE
0
1.5 V
1.5 V
excess of 100 mA.
ground and tester common.
Z
Z
3.5V Vth
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
4. Actualtest conditions may vary from
b. Ground and VCC supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified. socket or contactor fingers.
V
OH*
1
0V Vth
VOL*
Measured VOL with IOH = –10mA and IOL = 10mA
V
OH* Measured VOH with IOH = –10mA and IOL = 10mA
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by:
compensatefor inductiveground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements ofall parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 20 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Video Imaging Products
08/16/2000–LDS.43881-J
8
LOGIC [ LOGIC DEVICES INCORPORATED ]
