LF43168
DEVICES INCORPORATED
Dual 8-Tap FIR Filter
FIGURE 5. DECIMATING, EVEN-SYMMETRIC COEFFICIENT FILTER CONFIGURATIONS
N = Delay Length (Decimation Factor)
N = Delay Length (Decimation Factor)
N
N
N
N
N
N
N
N
N
Delay Stage N – 1 Output
N
DATA IN
N
N
DATA IN
A
B
A
B
A
B
A
B
A
B
A
B
A
B
A
B
B + A
B + A
B + A
B + A
B + A
B + A
B + A
B + A
COEF 0
COEF 1
COEF 2
COEF 3
COEF 0
COEF 1
COEF 2
COEF 3
EVEN-TAP FILTER
ODD-TAP FILTER
FIGURE 6. ODD-SYMMETRIC COEFFICIENT FILTER CONFIGURATIONS
N = Delay Length (Decimation Factor)
N
N
N
N
DATA IN
DATA IN
N
N
A
B
A
B
A
B
A
B
B – A
B – A
B – A
B – A
A
B
A
B
A
B
A
B
B – A
B – A
B – A
B – A
COEF 0
COEF 1
COEF 2
COEF 3
COEF 0
COEF 1
COEF 2
COEF 3
EVEN-TAP FILTER (NO DECIMATION)
DECIMATING, EVEN-TAP FILTER
Figure 5 shows the two possible
configurations when the device is
programmed as a decimating, even-
symmetric coefficient filter. The delay multipliers on different CLK cycles for
length of the decimation registers will filters with more than eight taps. Note
be equal to the decimation factor that
the device is programmed for. Since
only four coefficients (effectively
ers on a clock cycle, it may be neces-
sary (depending on the coefficient set)
to change the coefficients fed to the
Odd-Symmetric Coefficient Filters
Figure 6 shows the two possible
configurations when the device is
programmed for odd-symmetric
coefficients. Note that odd-tap, odd-
symmetric coefficient filters are not
possible.
that for the odd-tap filter, the middle
coefficient of the coefficient set must
be divided by two to get the correct
eight) can be sent to the filter multipli- result.
Video Imaging Products
03/28/2000–LDS.43168-H
8
LOGIC [ LOGIC DEVICES INCORPORATED ]
