LF43168
DEVICES INCORPORATED
Dual 8-Tap FIR Filter
the reverse decimation path, TXFR
would have to be set LOW once every
8 CLK cycles. Once a data block size
has been established (by asserting
TXFR at the proper frequency),
changing the frequency or phase of
TXFR assertion will cause unknown
results.
Decimation
Accumulators
The multiplier outputs are fed into an
Decimation by N is accomplished by
only reading the LF43168’s output once accumulator. Each filter has its own
every N clock cycles. For example, to
decimate by 10, the output should
only be read once every 10 clock
cycles. When not decimating, the
maximum number of taps possible
accumulator. The accumulator can be
set to accumulate the multiplier
outputs or sum the multiplier outputs
and send the result to the accumulator
output register. When ACCEN is
HIGH, both accumulators are enabled
If data should be passed to the reverse with a single filter in dual filter mode
decimation path with the order
is eight. When decimating by N, there for accumulation and writing to the
unchanged, Data Reversal Mode
should be disabled by setting bit 4 of
Control Register 1 to “1” and TXFR
must be set LOW. When Data Rever-
sal is disabled, data from the forward
decimation path is written into the
data feedback decimation register.
The output of this register sends data
to the reverse decimation path. The
delay length of this register is the
same as the forward and reverse
decimation register's delay length.
are N – 1 clock cycles between output
readings when the filter output is not
read. These extra clock cycles can be
used to calculate more filter taps. As
the decimation factor increases, the
accumulator output registers is
disabled (the registers hold their
values). When ACCEN goes LOW,
accumulation is halted (by sending
zeros to the accumulator feedback
number of available filter taps increases inputs) and writing to the accumula-
also. When programmed to decimate
by N, the number of filter taps for a
single filter in dual filter mode increases
to 8N.
tor output registers is enabled.
Mux/Adder
When the LF43168 is configured as
two FIR filters, the Mux/ Adder is
used to determine which filter drives
the output port. When the LF43168 is
configured as a single FIR filter, the
Mux/ Adder is used to sum the
Arithmetic Logic Units
When the LF43168 is configured to
operate as a single FIR filter, the
forward and reverse decimation paths
in filters A and B are cascaded together.
The data feedback section in filter B
routes data from the forward decima-
tion path to the reverse decimation
path. The configuration of filter B's
feedback section determines how data
is sent to the reverse decimation path.
Data going through the feedback
section in filter A is sent through the
decimation register.
The ALUs can perform the following
operations: B + A, B – A, pass A, pass
B, and negate A (–A). If FWRD is
LOW, the forward decimation path
provides the A inputs to the ALUs. If
FWRD is HIGH, the A inputs are set to and 20-bit coefficients or 20-bit data
"0". If RVRS is LOW, the reverse and 10-bit coefficients are required,
decimation path provides the B inputs the Mux/ Adder can facilitate this by
outputs of the two filters and send the
result to the output port. If 10-bit data
to the ALUs. If RVRS is HIGH, the B
inputs are set to "0". FWRD, RVRS,
scaling filter B’s output by 2–10 before
being added to filter A’s output.
and the filter configuration determine MUX1-0 determines what function the
which ALU operation is performed. If Mux/ Adder performs (see Table 3).
FWRD and RVRS are both set LOW,
The Mux/ Adder is also used to round
and the filter is set for even-symmetric
The point at which data from the
forward decimation path is sent to the
data feedback section is determined
by whether the filter is set to have an
even or odd number of filter taps. If
the filter is set to have an even number
of taps, the output of the third for-
ward decimation register is sent to the
feedback section. If the filter is set to
have an odd number of taps, the data
that will be output from the third
forward decimation register on the
next CLK cycle is sent to the feedback
section.
the output data before it is sent to the
coefficients, the ALU will perform the
output port. Output data is rounded by
B + A operation. If FWRD and RVRS
adding a “1” to the bit position selected
are both set LOW, and the filter is set
using bits 5-8 of Control Register 1 (see
for odd-symmetric coefficients, the
Table 2). For example, to round the
ALU will perform the B – A operation.
If FWRD is set LOW, RVRS is set
HIGH, and the filter is set for even-
symmetric coefficients, the ALU will
perform the pass A operation. If
FWRD is set LOW, RVRS is set HIGH,
and the filter is set for odd-symmetric
coefficients, the ALU will perform the
negate A operation. If FWRD is set
HIGH, RVRS is set LOW, and the filter
is set for either even or odd-symmetric
coefficients, the ALU will perform the
pass B operation.
TABLE 3. MUX1-0 FUNCTION
MUX1-0
FUNCTION
00
Filter A + Filter B
(Filter B Scaled by 2–10
)
01
10
11
Filter A + Filter B
Filter A
Filter B
Video Imaging Products
03/28/2000–LDS.43168-H
6
LOGIC [ LOGIC DEVICES INCORPORATED ]
