LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
FIGURE 12. SYMMETRIC COEFFICIENT SET EXAMPLES
8 7 6 5
8 7 6 5 4 3 2 1
7 6 5 4 3 2 1
4 3 2 1
Even-Tap, Even-Symmetric
Coefficient Set
Odd-Tap, Even-Symmetric
Coefficient Set
Even-Tap, Odd-Symmetric
Coefficient Set
FIGURE 13. I/D REGISTER DATA PATHS
Delay Stage N–1
Delay Stage N
A
B
A
B
A
B
A
B
A
B
A
B
ALU
ALU
ALU
ALU
ALU
ALU
COEF 7
2
COEF 7
2
COEF 7
COEF 6
COEF 6
COEF 6
EVEN-TAP MODE
ODD-TAP MODE
ODD-TAP INTERLEAVE MODE
The ALUs can perform two operations:
A+B and B–A. Bit 0 of Configuration
Register 0determines the operation of
the ALUs in Filter A.
TheInterleave/ DecimationRegisters(I/ D
Registers)feed theALUinputs. They
allow the device to filter up to sixteen data
setsinterleaved into thesamedata stream
without having to separate the data sets.
The I/ D Registers should be set to a length N–1 clock cycles when the filter’s output is
equaltothenumber ofdata setsinter-
leavedtogether.
clock cycles. Thedevicesupportsdecima-
tion up to 16:1. With no decimation, the
maximum numberoffiltertapsissixteen.
When decimatingbyN,thenumberof
filter tapsbecomes16N becausethereare
Bit 0ofConfiguration Register 2deter-
mines the operation of the ALUs in Filter
not being read. The extra clock cycles are
used tocalculatemorefilter taps.
B. A+B is used with
even-
symmetric coefficient sets. B–A is used
with odd-symmetriccoefficientsets.
For example, iftwo data setsareinter-
leaved together,theI/ DRegistersshould
be set to a length of two. Bits 1 through 4 of decimation factor. For example, when
Configuration Register1and Configura-
tion Register 3determinethelength ofthe
I/ DRegistersin Filters A and Brespec-
tively.
When decimating, the I/ D Registers
should be set to a length equal to the
Also, either the A or B operand may be
set to 0. Bits 1 and 2 of Configuration
Register 0 and Configuration Register 2
control the ALU inputs in
Filters A and Brespectively. A+0or B+0
areused with asymmetriccoefficient
sets.
performing a 4:1decimation, the I/ D
Registers should be set to a length of
four. When decimation is disabled or
when only one data set (non-interleaved
data) is fed into the device, the I/ D
Registers should be set to a length of
one.
The I/ D Registers also facilitate using
decimation toincreasethenumberoffilter
taps. Decimation by N is accomplished by
readingthefilter’soutputonceeveryN
Interleave/DecimationRegisters
Video Imaging Products
08/16/2000–LDS.3320-N
2-10
LOGIC [ LOGIC DEVICES INCORPORATED ]
