LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
RIN11-0 or DIN11-0 can be the data
input for Filter B. The Filter B input is
determined by Bit 2 in Configuration
Register 5. DOUT15-0 is the data
output for Filter A. COUT11-0 and
ROUT3-0 together form the data output
for Filter B. COUT11-0 is the twelve
least significant bits and ROUT3-0 is
the four most significant bits of the
16-bit Filter B output.
Matrix-vector Multiply Mode
In this mode, the LF3320 can be
configured to multiply a square matrix
of maximum size N (N = 8 or 16),
multiplied by a matrix-vector of
maximum size [8,1] or [16,1]. The
mathematical representation for this
operation is in Figure 7. When config-
ured in the dual filter mode, the LF3320
can process two matrix-vector multipli-
ers simultaneously (i.e. [8x8][8x1]). In
the single filter mode, the LF3320 can
process a single matrix-vector multiply
(i.e. [16x16][16x1]). This mode of
operation allows the user to organize
data values (e.g. pixels) into an array
(e.g. blocks). This function is useful for
any application requiring the opera-
tion of matrix multiplication; a func-
tion that is used when generating
Discrete Cosine Transform coefficients
(DCT) for the purpose of further
processing.
When configuring the LF3320 for an
[8x8][8x1] matrix-vector operation, the
coefficient banks will require 8 coeffi-
cient sets to be loaded into the coefficient
memory banks; each coefficient set will
have 8, 12-bit coefficients. The input
data, [8x1] column-vector, will be loaded
through DIN11-0 for Filter A; either
RIN11-0 or DIN11-0 can be the data
input for Filter B. Conversely, when
configured for a [16x16][16x1]
matrix-vector operation, the coefficient
banks will require 16 coefficient sets to
be loaded into the coefficient memory
banks; each coefficient set will have 16,
12-bit coefficients. The input data,
[16x1] column-vector, will be loaded
through DIN11-0.
To configure the LF3320 for
matrix-vector multiplication, bit 4 of
Configuration Register 5 must be set to
1 (Table 7). The configuration for
single filter mode or dual filter mode
will still apply. Writing 012H or 016H
to Configuration Register 5 will
configure the device for dual filter
mode, [8x8][8x1] matrix-vector multi-
plication. Subsequently, writing 014H
to Configuration Register 5 will
configure the device for single filter
OPERATIONAL MODES
Single Filter Mode
In this mode, the device operates as a
single FIR filter (see Figure 4). It can be
configured to have as many as 32 taps if
symmetric coefficient sets are used. If
asymmetric coefficient sets are used, the
device can be configured to have as
many as 16 taps. Cascade ports are
provided to facilitate cascading multiple
devices to increase the number of filter
taps. Bit 1 in Configuration Register 5
determines the filter mode. In Single
Filter Mode, DIN
11-0
is the data input
for the filter and DOUT
15-0
is the data
output for the filter.
Dual Filter Mode
In this mode, the device operates as
two separate FIR filters (see Figure 5).
Each filter can be configured to have as
many as 16 taps if symmetric coeffi-
cient sets are used. If asymmetric
coefficient sets are used, each filter can
be configured to have as many as 8
taps. In Dual Filter Mode, DIN11-0 is
the data input for Filter A. Either
F
IGURE
6. M
ATRIX
-
VECTOR
M
ULTIPLY
M
ODE
N
DIN
11-0
RIN
11-0
12
0
A
B
A
0
B
A
0
B
A
0
B
ALU
ALU
ALU
ALU
F
IGURE
7. M
ATRIX
E
QUATION
C = COEFFICIENTS
D = DATA INPUT
R = DATA OUTPUT
TXFRA
TXFRB
12
COEF (N-1)
N
COEF 2
12
12
COEF 1
12
COEF 0
C
00
C
01
C
02
R
0
C
10
C
11
C
12
R
1
R
2
= C
20
C
21
C
22
R
i
C
i0
C
i1
C
i2
(N-1)
C
0j
C
1j
C
2j
C
ij
D
0
D
1
D
2
D
i
R
i
Dual Filter Mode, N=8
Single FIlter Mode, N=16
32
=
C
ij
D
i
i=0
For j=0,1,2,...,(N-1)
N=8 or 16
Video Imaging Products
2-6
08/16/2000–LDS.3320-N
LOGIC [ LOGIC DEVICES INCORPORATED ]
