LF3304
DEVICES INCORPORATED
Dual Line Buffer/FIFO
the data presented on LENGTH11-0 is
loaded intothedeviceon theactiveedgeof
WCLKA in conjunction with LDA being
driven LOW. Tosetthelength ofRAM
Array B the data presented on
LINE BUFFER MODE
SIGNAL DEFINITIONS
TABLE 1. DEVICE CONFIGURATION
MODE1-0
Mode Select
Dual Line Buffer
Cascaded Line Buffer
Dual FIFO
Power
0
0
1
1
0
1
0
1
VCC and GND
LENGTH11-0 is loaded into the device
on the active edge of WCLKB in
+3.3 V power supply. All pins must
be connected.
conjunction with LDB being driven
LOW. If an equal length is desired for
both RAM Arrays, the data presented
on LENGTH11-0 is loaded into the
device on the active edge of WCLK
(WCLKA and WCLKBtied together)in
conjuction with LDx (LDA and LDB
tied together)being driven LOW.
Reserved
Clocks
delay mode, RWA and RRA should be
broughtLOWtoproperlyresettheWrite
and Read pointers.
WCLKA — Write Clock A
WCLKA and RCLKA must be tied
together for RAM Array A toproperly
operate as a Line Buffer. The rising edge
ofxCLKA strobes allappropriate
enabled registers.
RENA — Read Enable B
In Line Buffer mode, RENA must be
kept LOW.
MODE1-0 — Mode Select
Themodeselectinputsdeterminethe
operating modeoftheLF3304(Table1)for
data being input on the next clock cycle.
When switchingbetween modes,the
internal pipeline latencies of the device
mustbeobserved. Afterswitching
operatingmodes,eithertheusermust
allow enough clock clycles to pass to flush
the internal RAM Array or RWx and RRx
mustbedrivenLOWtogetherbeforevalid
data will appear on the outputs.
RCLKA — Read Clock A
WENB — Write Enable B
See WCLKA description.
Driving WENBLOW placesthedevicein
programmabledelaymodeand driving
WENB HIGH places RAM Array B in
recirculatemode(programmablecircular
buffer). When in recirculatemode,the
write pointer position remains fixed
while data on BIN11-0 is ignored. When
switching back from recirculate mode to
delay mode, RWB and RRB should be
brought LOW to properly reset theWrite
and Read pointers.
WCLKB — Write Clock B
WCLKB and RCLKB must be tied
together for RAM Array Bto properly
operate as a Line Buffer. The rising
edge ofxCLKBstrobes allappropriate
enabled registers.
RCLKB — Read Clock B
Controls
See WCLKBdescription.
LDA — RAM Array A Load
RENB — Read Enable B
Inputs
When LDA is LOW, data on
LENGTH11-0 is latched in the length
register on the rising edge of xCLKA.
In Line Buffer mode, RENB must be
kept LOW.
AIN11-0 — Data Input A
AIN11-0 is the 12-bit registered data
input port.
RWA — Reset Write A
LDB — RAM Array B Load
The write address pointer is reset to the
first physical location when RWA is set
LOW. After power up, the LF3304
requires a Reset Write for initialization
because the write address pointer is not
defined at that time.
When LDB is LOW, data on
LENGTH11-0 is latched in the length
register on the rising edge of xCLKB.
BIN11-0 — Data Input B
BIN11-0 is the 12-bit registered data
input port.
WENA — Write Enable A
LENGTH11-0 — Line Buffer Length
Driving WENA LOW placesthedevicein
programmabledelaymodeand driving
WENA HIGH placesRAM Array A in
recirculatemode(programmablecircular
buffer). When in recirculatemode,the
write pointer position remains fixed while
data on AIN11-0 is ignored. When
RRA — Reset Read A
The 12-bit value is used to specify the
length ofeach oftheRAM Arrays. An
integer value ranging from 0 to 4095 is
used to select a delay ranging from 2 to
4097 clock cycles. The value placed on
LENGTH11-0 is equal to the desired delay
minus8. Tosetthelength ofRAMArrayA
The read address pointer is reset to the
first physical location when RRA is set
LOW. After power up, the LF3304
requires a Reset Read for initialization
because the read address pointer is not
defined at that time.
switchingbackfrom recirculatemodeto
Video Imaging Products
8
08/16/2000–LDS.3304-F
2
LOGIC [ LOGIC DEVICES INCORPORATED ]
