LF2301
DEVICES INCORPORATED
Image Resampling Sequencer
F
IGURE
1. I
MAGE
T
RANSFORMATION
S
YSTEM
(ITS)
IMAGE DATA IN
12
SIGNAL DEFINITIONS
Power
Vcc and GND
+5V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all
enabled registers.
Inputs
P
11-0
— Parameter Register Data Input
P
11-0
is the 12-bit Parameter Register
Data input port. P
11-0
is latched on
the rising edge of CLK.
B
3-0
— Parameter Register Address Input
B
3-0
is the 4-bit Parameter Register
Address input port. B
3-0
is latched on
the rising edge of CLK.
Outputs
X
11-0
— Source Address Output
X
11-0
is the 12-bit registered Source
Address output port.
CA
7-0
—
Coefficient Address Output
CA
7-0
is the 8-bit registered Coeffi-
cient Address output port.
U
11-0
— Target Address Output
U
11-0
is the 12-bit registered Target
Address output port.
Controls
INIT — Initialize
When INIT is HIGH for a minimum of
two clock cycles, the control logic is
cleared and initialized for the start of a
new image transformation. When
INIT goes LOW, normal operation
begins after two clock cycles. INIT is
latched on the rising edge of CLK.
WEN
—
Write Enable
When
WEN is LOW,
data latched into
the device on P
11-0
is loaded into the
preload register addressed by the data
P
11-0
B
3-0
INIT, LDR,
WEN, NOOP, OETA
12
4
5
X
11-0
LF2301
Row
Address
Generator
(X)
CA
7-0
8
12
24
ACC
UWRI
U
11-0
12
INTER
END
SOURCE
IMAGE
RAM
12
X
ACC
INTERPOLATION
COEFFICIENT
RAM
LMA1009/2009
12 x 12 bit
Multiplier-
Accumulator
X,Y,P
D
OUT
12
8
12
Y
CA
7-0
LF2301
Column
Address
Generator
(Y)
12
12
24
Y
11-0
V
11-0
INTER
END
DESTINATION
IMAGE
RAM
12
CLK
IMAGE DATA OUT
latched into the device on B
3-0
. When
WEN is HIGH, data cannot be loaded
into the preload registers and their
contents will not be changed. WEN is
latched on the rising edge of CLK.
LDR — Load Data Register
When LDR is HIGH, data in all
preload registers is latched into the
Transformation Parameter Registers.
When LDR is LOW, data cannot be
loaded into the Transformation
Parameter Registers and their contents
will not be changed. LDR is latched
on the rising edge of CLK.
ACC — Accumulate
The registered ACC output initializes
the accumulation register of the
external multiplier-accumulator. At
the start of each interpolation “walk,”
ACC goes LOW for one cycle effec-
tively clearing the storage register by
loading in only the new first product.
ACC from either the row or column
LF2301 may be used.
UWRI — Target Memory Write Enable
The Target Memory Write Enable goes
LOW for one clock cycle after the end
of each interpolation “walk.” When
OETA is HIGH, this registered output
is forced to the high-impedance state.
UWRI from either the row or column
LF2301 may be used.
INTER — Interconnect
When two LF2301s are used to form
an ITS, the END flag on each device
is connected to INTER on the other
device. The END flag from the row
device indicates an “end of line” to the
column device. The END flag from the
column device indicates a “bottom of
frame” to the row device, forcing a
reset of the address counter.
NOOP — No Operation
When NOOP is LOW, the clock is
overridden holding all address
generators in their current state. X
11-0
and CA
7-0
are forced to the high-
Video Imaging Products
2-2
08/16/2000–LDS.2301-H
LOGIC [ LOGIC DEVICES INCORPORATED ]
