LF2272
DEVICES INCORPORATED
Colorspace Converter/
Corrector (3 x 12-bits)
SIGNAL DEFINITIONS
Power
TABLE 2. COEFFICIENT INPUTS
TABLE 3. COEFF. REG. UPDATE
INPUT PORT
REG. AVAILABLE
KA1, KA2, KA3
KB1, KB2, KB3
KC1, KC2, KC3
CWEL1-0
COEFFICIENT SET
Hold All Registers
KA1, KB1, KC1
KA2, KB2, KC2
KA3, KB3, KC3
VCC and GND
KA
KB
KC
00
01
10
11
+5 V power supply. All pins must be
connected.
Clock
Outputs
CLK — Master Clock
X11-0, Y11-0, Z11-0 — Data Outputs
The rising edge of CLK strobes all
enabled registers. All timing specifi-
cations are referenced to the rising
edge of CLK.
X, Y, and Z are the 12-bit registered
data output ports.
Controls
Inputs
CWEL1-0 — Coefficient Write Enable
A11-0, B11-0, C11-0 — Data Inputs
The registered coefficient write enable
inputs determine which internal
coefficient register set to update
(Table 3) on the next clock cycle.
A, B, and C are the 12-bit registered
data input ports. Data presented to
these ports is latched into the multi-
plier input registers.
KA9-0, KB9-0, KC9-0 — Coefficient Inputs
KA, KB, and KC are the 10-bit regis-
tered coefficient input ports. Data
presented to these ports is latched into
the corresponding internal coefficient
register set defined by CWEL1-0
(Table 3) on the next rising edge of
CLK. Table 2 shows which coefficient
registers are available for each coeffi-
cient input port.
Video Imaging Products
08/16/2000–LDS.2272-I
3
LOGIC [ LOGIC DEVICES INCORPORATED ]
