LF2249
DEVICES INCORPORATED
12 x 12-bit Digital Mixer
synchronous operation between the
incoming data and all available
control functions. The LF2249 oper-
ates at a clock rate of 40 MHz over the
full commercial temperature and
supply voltage ranges.
DETAILED VIEW OF BLOCK DIAGRAM OUTLINED AREA
ADEL3-0
4
A
11-0
ENA
12
Because of its flexibility, the LF2249 is
ideally suited for applications such as
image switching and mixing, digital
quadrature mixing and modulating,
FIR filtering, and arithmetic function
and waveform synthesis.
R1
R2
SIGNAL DEFINITIONS
Power
VCC and GND
CLK
R16
+5 V power supply. All pins must be
connected.
16 : 1
12
Clock
CLK — Master Clock
The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.
FIGURE 1A. INPUT FORMATS
Data Input
Inputs
11 10 9
8
7
6
5
4
3
2
1
0
A11-0–D11-0 — Data Inputs
–211 210 29 28 27 26 25 24 23 22 21 20
A11-0–D11-0 are 12-bit data input regis-
ters. Data is latched into the input reg-
isters on the rising edge of CLK. The
contents of the input registers are
clocked into the top of the correspond-
ing 16-stage pipeline delay (pushing the
contents of the register stack down one
register position) on the next clock cycle
if the pipeline register stack is enabled.
The LSBs are A0-D0 (Figure 1a).
(Sign)
Cascade Input
15 14 13 12 11 10 9
–223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28
8
7
6
5
4
3
2
1
0
(Sign)
FIGURE 1B. OUTPUT FORMATS
Sum Output (Upper 16 bits)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CAS15-0 — Cascade Data Input
–223 222 221 220 219 218 217 216 215 214 213 212 211 210 29 28
CAS15-0 is the 16-bit cascade data input
port. Data is latched into the register on
the rising edge ofCLK. The LSBis CAS0
(Figure 1a).
(Sign)
Sum Output (Lower 16 bits)
15 14 13 12 11 10 9
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
8
7
6
5
4
3
2
1
0
Video Imaging Products
08/16/2000–LDS.2249-J
2
LOGIC [ LOGIC DEVICES INCORPORATED ]
