LF2247
DEVICES INCORPORATED
Image Filter with Coefficient RAM
F
IGURE
2.
S
ERIAL
D
ATA
F
ORMAT
FIRST 16-BIT WORD
SECOND 16-BIT WORD
the DN register on the rising edge of
CLK. When ENB
N
is HIGH, data on
DN
9-0
is not latched into the DN
register and the register contents will
not be changed.
ENBA — Row Address Input Enable
The ENBA input allows the row
address register to be updated on each
clock cycle. When ENBA is LOW,
data on A
4-0
is latched into the row
address register on the rising edge of
CLK. When ENBA is HIGH, data on
A
4-0
is not latched into the row
address register and the register
contents will not be changed.
OEN — Output Enable
When OEN is LOW, S
15-0
is enabled
for output. When OEN is HIGH, S
15-0
is placed in a high-impedance state.
OCEN — Clock Enable
When OCEN is LOW, data in the pre-
mux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register
is held preventing the output
register’s contents from changing (if
FSEL does not change). Accumulation
continues internally as long as ACC is
HIGH, despite the state of OCEN.
FSEL — Format Select
When FSEL is LOW, the data input
during the current clock cycle is
assumed to be in fractional two’s
complement format, and the upper 16
bits of the accumulator are presented
at the output. Rounding of the
accumulator result to 16 bits is per-
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 X X X X X 0 0 0 1 0 0 0 1 1 0 0
ROW
ADDRESS
DATA FOR
COEFFICIENT REGISTER 4
DON'T
CARES
DATA FOR
COEFFICIENT REGISTER 3
1
2
3
4
THIRD 16-BIT WORD
FOURTH 16-BIT WORD
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
X X X X X 0 0 1 1 0 1 0 0 1 0 0 X X X X X 1 1 1 1 1 1 0 0 1 0 0
DON'T
CARES
DATA FOR
COEFFICIENT REGISTER 2
DON'T
CARES
DATA FOR
COEFFICIENT REGISTER 1
SHOWN IS SERIAL DATA STREAM TO LOAD ROW ADDRESS 2 WITH:
COEFFICIENT REGISTER 1 = 7E4
COEFFICIENT REGISTER 2 = 1A4
COEFFICIENT REGISTER 3 = 08C
COEFFICIENT REGISTER 4 = 7EC
5
6
7
8
9
10
11
formed if the accumulator control
input ACC is LOW. When FSEL is
HIGH, the data input is assumed to be
in integer two’s complement format,
and the lower 16 bits of the accumula-
tor are presented at the output. No
rounding is performed when FSEL is
HIGH.
ACC — Accumulator Control
The ACC input determines whether
internal accumulation is performed on
the data input during the current
clock cycle. If ACC is LOW, no
accumulation is performed, the prior
accumulated sum is cleared, and the
current sum of products is output. If
FSEL is also LOW, one-half LSB
rounding to 16 bits is performed on
the result. When ACC is HIGH, the
emerging product is added to the sum
of the previous products, without
additional rounding.
SEN — Serial Input Enable
The SEN input enables the shifting of
serial data through the registers in the
coefficient register file. When SEN is
LOW, serial data on SDIN is shifted
into the coefficient register file on the
rising edge of SCLK. SEN must
remain LOW until all four coefficients
have been clocked in. SEN does not
need to be pulsed between consecu-
tive data sets. It can remain LOW
while the entire register file is loaded
by a constant bit stream. When SEN is
HIGH, data can not be shifted into the
register file and the register file’s
contents will not be changed. When
enabling the coefficient register file for
serial data input, the LF2247 requires
a HIGH to LOW transition of SEN in
order to function properly. Therefore,
SEN needs to be set HIGH immedi-
ately after power up to ensure proper
operation of the serial input circuitry.
Video Imaging Products
3
08/16/2000–LDS.2247-H
LOGIC [ LOGIC DEVICES INCORPORATED ]
