LF2246
DEVICES INCORPORATED
11 x 10-bit Image Filter
TABLE 1. INPUT REGISTER CONTROL
INPUT REGISTER
FIGURE 1A. INPUT FORMATS
Data
Coefficient
ENB1-4 ENSEL
HELD
Fractional Two’s Complement (FSEL = 0)
1
1
0
1
0
X
Data ‘N’
9
8
7
2
1
0
10
9
8
2
1
0
Coefficient ‘N’
None
–20 2–1 2–2
2–7 2–8 2–9
–21 20 2–1
2–7 2–8 2–9
(Sign)
(Sign)
X = “Don’t Care”
‘N’ = 1, 2, 3, or 4
Integer Two’s Complement (FSEL = 1)
9
8
7
2
1
0
10
9
8
2
1
0
–29 28 27
22 21 20
–210 29 28
22 21 20
OCEN — Clock Enable
(Sign)
(Sign)
When OCEN is LOW, data in the pre-
mux register (accumulator output) is
loaded into the output register on the
next rising edge of CLK. When OCEN
is HIGH, data in the pre-mux register is
held preventing the output register’s
contents from changing (if FSEL does
not change). Accumulation continues
internally as long as ACC is HIGH,
despite the state of OCEN.
FIGURE 1B. OUTPUT FORMATS
Fractional Two’s Complement (FSEL = 0)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
–26 25 24 23 22 21 20 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9
(Sign)
Integer Two’s Complement (FSEL = 1)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
–215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
(Sign)
FSEL — Format Select
When the FSEL input is LOW, the data
input during the current clock cycle is
assumed to be in fractional two’s
complement format, and the upper 16
bits of the accumulator are presented at
the output. Rounding of the accumula-
tor result to 16 bits is performed if the
accumulator control input ACC is
LOW. When FSEL is HIGH, the data
input is assumed to be in integer two’s
complement format, and the lower 16
bits of the accumulator are presented at
the output. No rounding is performed
when FSEL is HIGH.
SIGNAL DEFINITIONS
Controls
ENB1–ENB4 — Input Enable
Power
VCC and GND
The ENBN (N = 1, 2, 3, or 4) input allows
eitherorboththeDN andCN registersto
be updated on each clock cycle. When
ENBN is LOW, registers DN and CN are
both strobed by the next rising edge of
CLK. When ENBN is HIGH and ENSEL
is LOW, register DN is strobed while
register CN is held. If both ENBN and
ENSEL are HIGH, register DN is held,
and register CN is strobed (Table 1).
+5 V power supply. All pins must be
connected.
Clock
CLK — Master Clock
The rising edge of CLK strobes all en-
abled registers. All timing specifica-
tions are referenced to the rising edge of
CLK.
ENSEL — Enable Select
ACC — Accumulator Control
Inputs
D19–0–D49–0 — Data Input
The ENSEL input in conjunction with
the individual input enables ENB1–
ENB4 determines whether the data or
the coefficient input registers will be
held on the next rising edge of CLK
(Table 1).
The ACC input determines whether in-
ternal accumulation is performed on
the data input during the current clock
cycle. If ACC is LOW, no accumulation
is performed, the prior accumulated
sum is cleared, and the current sum of
productsisoutput. IfFSELisalsoLOW,
one-half LSB rounding to 16 bits is per-
formed on the result. This allows sum-
mations without propagating roundoff
errors. When ACC is HIGH, the emerg-
ing product is added to the sum of the
previous products, without additional
rounding.
D1–D4 are 10-bit data input registers.
The LSB is DN0 (Figure 1a).
C110–0–C410–0 — Coefficient Input
C1–C4 are 11-bit coefficient input regis-
ters. The LSB is CN0 (Figure 1a).
OEN — Output Enable
When the OEN signal is LOW, the cur-
rent data in the output register is avail-
able on the S15–0 pins. When OEN is
HIGH, the outputs are in a high-imped-
ance state.
Outputs
S15–0 — Data Output
The current 16-bit result is available on
the S15–0 outputs (Figure 1b).
Video Imaging Products
08/16/2000–LDS.2246-K
2-12
LOGIC [ LOGIC DEVICES INCORPORATED ]
