ADVANCE INFORMATION L9D320G32BG6
2.0 Gb, DDR3, 64 M x 32 Integrated Module (IMOD)
TABLE 3 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED
Ball Assignments
Symbol Type
ODT
Description
Input
G7
On-Die Termination: ODT enables (when registered HIGH) and disables termination
resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT
is only applied to each of the following signals: DQ[63:0], LDQSx, LDQSx\, UDQSx,
UDQSx\, UDMx, and LDMx. The ODT input is ignored if disabled via the LOAD MODE
register command. ODT is referenced to VrefCA.
Input
F3
RESET\
RESET: An input control pin, active LOW referenced to Vss. The RESET\ input receiver
is a CMOS input defined as a rail to rail signal with DC HIGH ≥ 0.8 x Vcc and DC LOW
≤ 0.2 x VccQ. RESET\ assertion and de-assertion are asynchronous.
Data Strobe, LOW Byte (per WORD): Output, edge-aligned with READ data. Input,
center-aligned with WRITE data.
Input
Input
I/O
D5, C5,
K6, L6
LDQSx, LDQSx\
UDQSx, UDQSx\
C6, D6,
Data Strobe, HIGH Byte (per WORD): Output, edge-aligned with READ data. Input,
center-aligned with WRITE data.
L5, K5
D2, B3, D4
C2, D7, B8,
D9, B5
DQ0, DQ1, DQ2,
DQ3, DQ4, DQ5,
DQ6, DQ7
Data Input/Output: LOW Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ.
I/O
I/O
I/O
B6, B9, D8,
B7, C9, B4,
D3, B2
DQ8, DQ9, DQ10,
DQ11, DQ12, DQ13,
DQ14, DQ15
Data Input/Output: HIGH Byte, LOW WORD (WORD 1). Pin referenced to VrefDQ.
Data Input/Output: LOW Byte, WORD 2. Pin referenced to VrefDQ.
Data Input/Output: HIGH Byte, WORD 2. Pin referenced to VrefDQ.
Unpopulated, un-plated matrix location(s)
K2, M3, K4,
L2, K7, M8,
K9, M5
DQ16, DQ17, DQ18,
DQ19, DQ20, DQ21,
DQ22, DQ23
M6, M9, K8,
M7, L9, M4,
K3, M2
DQ24, DQ25, DQ26,
DQ27, DQ28, DQ29,
DQ30, DQ31
A1
unpopulated
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
9
Jul 08, 2009 LDS-L9D320G32BG6-A
LOGIC [ LOGIC DEVICES INCORPORATED ]
