L9D3256M72SBG2
PRELIMINARY INFORMATION L9D3256M80SBG2
18-20 Gb, DDR3, 256 M x 72/80 Integrated Module
STATE DIAGRAM
FIGURE 2 - SIMPLIFIED STATE DIAGRAM
CKE L
MRS, MPR,
Self
Power
applied
Reset
Procedure
Power
on
Initialization
write
refresh
leveling
SRE
ZQCL
MRS
SRX
REF
RESET
From any
state
ZQCL/ZQCS
ZQ
Calibration
Idle
Refreshing
PDE
PDX
ACT
Active
Power-
Down
Preharge
Power-
Down
Activating
PDX
PDE
CKE L
CKE L
Bank
Active
WRITE
READ
WRITE
READ
WRITE AP
WRITE
READ AP
READ
Writing
Reading
WRITE AP
READ AP
WRITE AP
READ AP
PRE, PREA
Writing
Reading
PRE, PREA
PRE, PREA
Preharging
Automatic
Sequence
Command
Sequence
ACT = ACTIVATE
PREA=PRECHARGE ALL
READ = RD, RDS4, RDS8
SRX = Self refresh exit
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
WRITE = WR, WRS4, WRS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
RESET = START RESET PROCEDURE
SRE = Self refresh entry
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
3
July 24, 2013 LDS-L9D3256MxxSBG2 Rev B
LOGIC [ LOGIC DEVICES INCORPORATED ]
