PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
FUNCTIONAL DESCRIPTION
GENERAL DESCRIPTION
The LOGIC Devices, 2.5Gb, DDR SDRAM IMOD, is one member of its
Integrated Module family. This family of Integrated memory modules
contains DDR3/DDR2 and DDR device definitions in three package foot-
prints including this 25mm2, a 16mm x 22mm package and a 25mm x
32mm footprint. This device, a high speed CMOS random-access, inte-
grated memory device based on use of (5) silicon devices each contain-
ing 536,870,912 bits. Each chip is internally configured as a quad-bank
SDRAM. Each of the chips 134, 217, 728 bit banks is organized as 8,192
rows by 1024 columns by 16bits. Each of the Silicon devices equates to
a WORD or DUAL-BYTES, each BYTE containing Data Mask and Data
Strobes.
READ and WRITE accesses to the DDR SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the registration of an ACTIVE
command which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command are used to select the
bank and row to be accessed (BA0 and BA1 select the bank, A0-A12 select the
row). The address bits registered coincident with the READ or WRITE com-
mand are used to select the starting column location for the burst access.
Prior to normal operation, the IMOD must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions and device operation.
The 2.5Gb DDR IMOD uses the double-data-rate (DDR) architecture to
achieve high-speed operation. The double-data-rate architecture is a
2n-prefetch architecture with an interface designed to transfer two data
words per clock cycle via the I/O pins. A single READ or WRITE access
for the 2.5Gb DDR IMOD effectively consists of a single 2n-bit wide, one
clock cycle transfer at the internal DRAM core and two corresponding
n-bit wide, one-half-clock cycle data transfers at the DQ (I/O) pins.
A bidirectional data strobe (DQSLx, DQSHx) is transmitted externally,
along with data, for use in data capture at the end-point receiver. DQSLx,
DQSHx are strobes transmitted by the DDR SDRAM during READ opera-
tions and by the memory controller during WRITE operations. Each
strobe, DQSLx, DQSHx control each of two bytes contained within each
of the (5) silicon chips contained in LDI’s IMOD.
INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner.
Operational procedures other than those specified may result in undefined
operation. Power must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the System VTT). VTT must be applied after VCCQ to avoid
device latch-up, which may cause permanent damage to the device. VREF
can be applied after VCCQ but is expected to be nominally coincident with VTT.
Except for CKE, inputs are not recognized as valid until after FREF is applied.
CKE during power-up is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven in normal operation
(by a READ access). After all power supply and reference voltages are stable,
and the clock is stable, the IMOD requires a 200us delay prior to applying an
executable command.
The 2.5Gb DDR SDRAM operated from a differential clock (CLKx, CLKx\);
the crossing of CLKx going HIGH and CLKx\ going LOW will be referred
to as the positive edge of CLK. Commands (address and control signals)
are registered at every positive edge of CLK. Input data is registered on
both edges of DQS, and output data is referenced to both edges of DQS,
as well as to both edges of CLK.
Once the 200us delay has been satisfied, a DESELECT or NOP command
should be applied, and CKE should be brought HIGH. Following the NOP com-
mand, a PRECHARGE ALL command should be applied. Next a LOAD MODE
REGISTER command should be issued for the extended mode register (BA1
LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1 both LOW) to reset the
DLL and to program the operating parameters. Two-hundred clock cycles are
required between the DLL reset and any READ command. A PRECHARGE
ALL command should then be applied, placing the device in the all banks idle
state.
READ and WRITE accesses to the DDR memory are burst oriented;
accesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident with the READ
or WRITE command are used to select the bank and the starting column
location for the burst access.
The DDR IMOD provides for programmable READ or WRITE burst
lengths of 2, 4, or 8 locations. An AUTO-PRECHARGE function may be
enabled to provide a self-timed row PRECHARGE that is initiated at the
end of the burst access.
Once in the idle state, two AUTO PRECHARGE cycles must be performed
t
( RFC must be satisfied). Additionally, a LOAD MODE REGISTER command
for the mode register with the reset DLL bit deactivated (i.e. to program operat-
ing parameters without resetting the DLL) is required. Following these require-
ments, the DDR IMOD is ready for normal operation.
The pipelined, multi-banked architecture of the DDR SDRAM architecture
allows for concurrent operations, therefore providing high effective band-
width, by hiding row PRECHARGE and activation time.
An AUTO REFRESH mode is provided, along with a power-saving power-
down mode.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
6
Feb 2, 2009 LDS-L9D125G80BG4-C