PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
Fig u r e 1 - mo D e re g is t e r DeFinition
BA1 BA0 An . . . A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus
1
n
n + 2 n + 1
. . .
9
8
7
6
5
4
3
2
1
0
Mode register
(Mx)
Operating mode
0
0
CAS Latency BT Burst length
M2 M1 M0 Burst Length
Mode Register Definition
Base mode register
Extended mode register
Reserved
Mn + 1
Mn + 2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Reserved
2
0
1
0
1
0
0
1
1
M3
0
Burst Type
Sequential
Interleaved
4
8
Reserved
1
Reserved
Reserved
Reserved
Reserved
Mn . . . M9 M8 M7 M6–M0 Operating Mode
0
0
–
0
0
–
0
0
–
0
1
–
0
0
–
Valid
Valid
–
Normal operation
Normal operation/reset DLL
All other states reserved
M6 M5 M4
CAS Latency
Reserved
Reserved
2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
3
Reserved
Reserved
2.5
Reserved
Note: 1. n is the most significant row address bit
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
9
Feb 2, 2009 LDS-L9D125G80BG4-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
