PreLIMINArY INforMAtIoN L9D125G80BG4
2.5 Gb, DDR - SDRAM Integrated Module (IMOD)
REGISTER DEFINITION
mo D e re g is t e r
Bu r s t le n g t h
Bu r s t t y P e
READ and WRITE accesses to the DDR IMOD
are burst oriented, with the burst length being
programmable, as shown in Figure 3. The
burst length determines the maximum number
of column locations that can be accessed for a
given READ or WRITE command. Burst lengths
of 2, 4, or 8 locations are available for both the
sequential and interleaved burst types.
The MODE REGISTER is used to define the spe-
cific mode of operation of the DDR IMOD. This
definition includes the selection of a burst length,
a burst type, a CAS latency as shown in Figure
2 and the operating mode, as shown in Figure 3.
The MODE REGISTER is programmed via the
MODE REGISTER SET command (with BA0=0
and BA1=0) and will retain the stored information
until it is programmed again or the device real-
izes a loss of power (except for bit A8 which is
self clearing).
Accesses within a given burst may be pro-
grammed to be either sequential or interleaved;
this is referred to as the burst type and is selected
via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the
starting column address, as shown in Table 1.
Reserved states should not be used, as unknown
operation or incompatibility issues with future
version may result.
Reprogramming the MODE REGISTER will not
alter the contents of the memory, provided it is
performed correctly. The MODE REGISTER
must be loaded (reloaded) when all banks are idle
and no bursts are in progress, and the controller
must wait the specified time before initiating the
subsequent operation. Violating either of these
requirements will result in unspecified operation.
MODE REGISTER bits A0-A2 specify the burst
length, A3 specifies the type of burst (sequential
or interleaved), A4-A6 specify the CAS latency,
and A7-A12 specify the operating mode.
When a READ or WRITE command is issued,
a block of columns equal to the burst length is
effectively selected. All accesses for that burst
take place within this block, meaning that the
burst will wrap within the block if a boundary is
reached. The block is uniquely selected by A1-Ai
when the burst length is set to two; by A2-Ai when
the burst length is set to four and by A3-Ai when
the burst length is set to eight. The remaining
(least significant) address bits are used to select
the starting location within the block. The pro-
grammed burst length applies to both the READ
and WRITE bursts.
ta B l e 1: Bu r s t DeFinition
Order of Accesses within a Burst
Burst Length Starting Column Address Type = Sequential
Type = Interleaved
Notes
1. For a burst length of two, A1-Ai selects
a two-data-element block; A0 selects the
starting column within the block.
2
A0
0
0-1
1-0
0-1
1-0
1
2. For a burst length of four, A2-Ai selects
a four-data-element block; A0-1 selects the
starting column within the block.
4
A1
0
A0
0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0
1
3. For a burst length of eight, A3-Ai selects
an eight-data-element block; A0-2 selects
the starting column within the block.
1
0
1
1
8
A2
0
A1
0
A0
0
4. Whenever a boundary of the block is
reached within a given sequence above,
the following access wraps within the block.
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
7
Feb 2, 2009 LDS-L9D125G80BG4-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
