PreLIMINArY INforMAtIoN L9D112G80BG4
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)
Pin/Ba l l lo c a t io n s /DeFinitions a n D Fu n c t io n a l De s c r iP t io n
BGA Locations
Symbol
Type
Description
F4, F16, G5, G15, K1,
Clock: CKx and CKx\ are differential clock inputs. All address and control input signals are
CNTL. Input
CKX,CKX\
K12, L2, L13, N6, M8
G4, G16, K2, K13, M6
sampled on the crossing of the positive edge of CKx and negative edge of CKx\. Output data
(DQ’s and DQS) is referenced to the crossings of the differential clock inputs.
Clock Enable: CKE controls the clock inputs. CKE High enables, CKE Low disables the clock
input pins. Driving CKE Low provides PRECHARGE POWER-DOWN. CKE is synchronous
for POWER-DOWN entry and exit, and for SELF-REFRESH entry CKE is asynchronous for
SELF-REFRESH exit and disabling the outputs. CKE must be maintained High throughout
READ and WRITE accesses. Input buffers are disabled during POWER-DOWN, input buffers
are disabled during SELF-REFRESH. CKE is an SSTL-2 input but will detect an LVCMOS
LOW level after VCC is applied.
CNTL. Input
CKEx
G1, G13, K4, K16, M12
Chip Select: CSx\ enables the COMMAND register(s) of each of the five (5) integrated
words. All commands are masked (registered) HIGH with CSx\ driven true. CSx\ provides for
external word/bank selection on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
CNTL. Input
CSX\
F12, G2, K15, L5, M11
F1, G12, L4, L16, M9
F2, F13, L15, M4, M10
E2, E4, E13, F15, M2,
M5, M7, M13, M15, N11
Row Address Strobe: Command input along with CASx\ and WEx\
CNTL. Input
CNTL. Input
CNTL. Input
CNTL. Input
RASX\
CASX\
WEX\
Column Address Strobe: Command input along with RASx\ and WEx\
WRITE (word): Command input along with CASx\ and RASx\
Input Data Mask: DQM is an input mask signal for WRITE operations. Input Data is masked
when DQML/Hx is sampled HIGH at time of a WRITE access DQML/Hx is sampled on both
edges of DQSL/Hx.
DQMLX,
DQMHX
E5, E6, E7, E10, E11,
F5, K5, L12, N5, N12
E12
Data Strobe: Output flag on READ data and Input flag on WRITE data. DQS is edge-aligned
with READ data, centered in WRITE data operations.
DQSLX,
DQSHX
Vref
Reference Voltage
Level REF
Input
A7, A8, A9, A10, B7, B8,
B9, B10, C7, C8, C9,
C10, D7
Address input: Provide the ROW address for ACTIVE commands and the COLUMN address
and AUTO PRE-CHARGE bit (A10) for READ/WRITE commands to select one location out of
the total array within a selected bank A10 sampled during a PRE-CHARGE command deter-
mines whether the PRE-CHARGE applies to one bank or all banks. The address inputs also
provide the OP-CODE during a MODE REGISTER SET command.
A0-A12
E8, E9
Bank Address input: define which BANK is active during a READ, WRITE, or PRE-CHARGE
command.
Input
BA0, BA1
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
4
Feb 2, 2009 LDS-L9D112G80BG4-C
LOGIC [ LOGIC DEVICES INCORPORATED ]
