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L9D112G80BG4E75 参数 Datasheet PDF下载

L9D112G80BG4E75图片预览
型号: L9D112G80BG4E75
PDF下载: 下载PDF文件 查看货源
内容描述: 1.2 GB , DDR - SDRAM集成模块 [1.2 Gb, DDR - SDRAM Integrated Module]
分类和应用: 内存集成电路动态存储器双倍数据速率时钟
文件页数/大小: 45 页 / 6016 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
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PreLIMINArY INforMAtIoN L9D112G80BG4  
1.2 Gb, DDR - SDRAM Integrated Module (IMOD)  
READ LATENCY  
Table 2 - Ca s la t e n c y  
Allowable Operating Frequency (MHz)  
The READ latency is the delay in clock cycles, between the registration of  
a READ command and the availability of the first bit of output data. The  
latency can be set to 2 or 2.5 clocks.  
Speed  
-10  
-8  
CAS Latency = 2  
CAS Latency = 2.5  
≤100  
≤83  
≤100  
≤125  
NA  
If a READ command is registered at clock edge [n], and the latency is  
[m] clocks, the data will be available by clock edge [n+m]. Table 2 indi-  
cates the operating frequencies at which each CAS latency setting can  
be used.  
≤125  
-75  
-6  
≤133  
≤166  
Reserved states should not be used as unknown operation or incompat-  
ibility with future versions may result.  
OPERATING MODE  
The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12, each set to zero, and bits A0-A6, set to the desired  
values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12, each set to zero, bit A8 set to one, and bits A0-A6, set to  
the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should  
always be followed by a LOAD MODE REGISTER command to select normal operating mode.  
All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because  
unknown operation or incompatibility from future versions may result.  
EXTENDED MODE REGISTER  
The EXTENDED MODE REGISTER controls functions beyond those controlled by the MODE REGISTER; these additional functions are DLL enable/disable,  
output drive strength, and QFC#. These functions are controlled via the bits shown in Figure 4. The EXTENDED MODE REGISTER command to the MODE  
REGISTER (with BA0=1, BA1=0) and the register will retain the stored information until it is programmed again or the device realizes loss of power. The  
enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the MODE REGISTER (BA0=BA1=LOW) to reset the DLL.  
The EXTENDED MODE REGISTER must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before  
initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.  
LOGIC Devices Incorporated  
www.logicdevices.com  
High Performance, Integrated Memory Module Product  
8
Feb 2, 2009 LDS-L9D112G80BG4-C