L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
FIGURE 1. FIFO MEMORY (DEPTH EXPANSION) BLOCK DIAGRAM
W
XO
R
Q
V
FF
EF
9
9
9
9
9
9
D
8-0
L8C20X
8-0
CC
XI FL
XO
FULL
FF
EF
EMPTY
L8C20X
XI FL
XO
FF
EF
L8C20X
RS
XI FL
TABLE 1. RESET AND RETRANSMIT (SINGLE DEVICE CONFIGURATION/WIDTH EXPANSION MODE)
INPUTS
INTERNAL STATUS
OUTPUTS
MODE
Reset
RS
0
RT
X
XI
0
Read Pointer
Location Zero
Location Zero
Increment
Write Pointer
Location Zero
Unchanged
Increment
EF
0
FF
1
HF
1
Retransmit
Read/Write
1
0
0
X
X
X
1
1
0
X
X
X
TABLE 2. RESET AND FIRST LOAD TRUTH TABLE (DEPTH EXPANSION/COMPOUND EXPANSION MODE)
INPUTS
INTERNAL STATUS
OUTPUTS
MODE
RS
0
RT
0
XI
(1)
(1)
(1)
Read Pointer
Write Pointer
Location Zero
Location Zero Disabled
X
EF
FF
1
Reset First Device
Reset All Others
Read/Write
Location Zero
0
0
X
0
1
Location Zero Disabled
X
1
1
(2)
X
OBSOLETE
(1) See Figure 1 (Depth Expansion Block Diagram)
(2) Unchanged
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
13
LOGIC [ LOGIC DEVICES INCORPORATED ]
