L8C201/202/203/204
DEVICES INCORPORATED
512/1K/2K/4K x 9-bit Asynchronous FIFO
SWITCHING CHARACTERISTICS Over Military Operating Range
ASYNCHRONOUS AND RESET TIMING (ns)
L8C201/202/203/204–
40
30
20
Symbol Parameter
Min Max Min Max Min Max
tRLRL
tRLQV
tRHRL
tRLRH
tRHQV
tRHQZ
tWLWL
tWLWH
tWHWL
tDVWH
tWHDX
tSLSH
tSLWL
tWHSH
tRHSH
tSHWL
tSLEL
Read Cycle Time (MHz)
50
40
30
Read Low to Output Valid (Access Time)
Read High to Read Low (Notes 8, 9)
Read Low to End of Read Cycle (Notes 8, 9)
Read High to Output Valid
40
25
30
20
20
10
40
5
10
30
5
10
20
5
Read High to Output High Z (Note 14)
Write Cycle Time (Note 9)
15
50
40
10
20
0
40
30
10
18
0
30
20
10
12
0
Write Low to Write High (Notes 8, 9)
Write High to End of Write Cycle (Notes 8, 9)
Data Valid to Write High (Notes 8, 9)
Write High to Data Change (Notes 8, 9)
Reset Cycle Time (Notes 9, 10)
40
50
40
40
10
30
40
30
30
10
20
30
20
20
10
Reset Low to Write Low (Notes 9, 10)
Write High to Reset High (Notes 9, 10)
Read High to Reset High (Notes 9, 10)
Reset High to Write Low (Notes 9, 10)
Reset Low to Empty Flag Low
50
50
50
40
40
40
30
30
30
tSLHH
tSLFH
Reset Low to Half-Full Flag High
Reset Low to Full Flag High
ASYNCHRONOUS READ AND WRITE OPERATION
t
RLRL
tRLRH
t
RLQV
tRHRL
tRLQV
R
8-0
W
t
RHQV
t
RHQZ
Q
DATA-OUT VALID
WLWL
DATA-OUT VALID
t
t
tWLWH
tWHWL
DVWH
tWHDX
D8-0
DATA-IN VALID
DATA-IN VALID
RESET TIMING
tSLWL
t
SLSH
RS
W
t
WHSH
t
SHWL
tRHSH
OBSOLETE
R
t
SLEL
EF
tSLHH, tSLFH
HF, FF
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
9
LOGIC [ LOGIC DEVICES INCORPORATED ]
