L7C108
L7C109
128K x 8 Static RAM
SWITCHING CHARACTERISTICS Over Operating Range
READ CYCLE Notes 5, 11, 12, 22, 23, 24 (ns)
L7C108/109
35/35-L
15/15-L
25/25-L
20/20-L
45/45-L
Min Max Min Max Min Max Min Max Min Max
Symbol Parameter
tAVAV
t$949
t$94;
t(/49
t(/4;
t(+4=
t*/49
t*/4;
t*+4=
tPU
15
20
25
35
45
Read Cycle Time
15
15
20
20
25
25
35
35
45
45
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Address Change to Output Change
3
3
3
3
3
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Output Enable Low to Output Valid
3
3
3
3
3
7
8
8
10
10
15
15
20
20
10
0
0
0
0
0
0
0
0
0
0
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2XWSXWꢀ(QDEOHꢀ+LJKꢀWRꢀ2XWSXWꢀ+LJKꢀ=ꢀꢆ1RWHVꢀꢂꢅꢏꢀꢂꢈꢉ
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6
6
10
15
20
READ CYCLE - ADDRESS CONTROLLED Notes 13, 14
tAVAV
ADDRESS
tAVQV
DATA OUT
PREVIOUS DATA VALID
tAVQX
DATA VALID
tPD
tPU
ICC
READ CYCLE - CE/OE CONTROLLED NOTES 13, 15
tAVAV
CE
t
EHQZ
t
ELQV
t
ELQX
OE
t
GHQZ
t
GLQV
t
GLQX
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
50%
t
PD
tPU
50%
Icc
1M Static RAMs
Feb 17, 2012 LDS-L7C108/9-G
LOGIC Devices Incorporated
www.logicdevices.com
4
LOGIC [ LOGIC DEVICES INCORPORATED ]
