L4C383
DEVICES INCORPORATED
16-bit Cascadable ALU (Extended Set)
F
IGURE
4A.
FTAB = 0, FTF = 0
From
Clock
Clock
C
0
S
4
-S
0
A, B
C
0
S
4
-S
0
ENA, ENB, ENF
Minimum cycle time
A
31
-A
16
To
©
F
©
Other
©
Other
©
Other
Setup time
Setup time
Setup time
Setup time
=
=
=
=
=
=
=
=
=
Calculated Specification Limit
Same as 16-bit case
(Clock
©
C
16
) + (C
0
©
Out)
(C
0
©
C
16
) + (C
0
©
Out)
(S
4
-S
0
©
C
16
) + (C
0
©
Out)
Same as 16-bit case
(C
0
©
C
16
) + (C
0
Setup time)
(S
4
-S
0
©
C
16
) + (C
0
Setup time)
Same as 16-bit case
(Clock
©
C
16
) + (C
0
Setup time)
B
15
-B
0
B
31
-B
16
A
15
-A
0
D
Q
D
Q
D
Q
D
Q
CLOCK
C
0,
S
4
–S
0
A
F
B
C
0
A
C
16
F
B
C
0
D
Q
CLOCK
16
D
Q
CLOCK
MOST
SIGNIFICANT
SLICE
16
F
31
-F
16
F
15
-F
0
LEAST
SIGNIFICANT
SLICE
F
IGURE
4B.
FTAB = 0, FTF = 1
From
Clock
Clock
C
0
C
0
S
4
-S
0
S
4
-S
0
A, B
C
0
S
4
-S
0
ENA, ENB, ENF
Minimum cycle time
To
©
F
©
Other
©
F
©
Other
©
F
©
Other
Setup time
Setup time
Setup time
Setup time
=
=
=
=
=
=
=
=
=
=
=
Calculated Specification Limit
(Clock
©
C
16
) + (C
0
©
F)
(Clock
©
C
16
) + (C
0
©
Out)
(C
0
©
C
16
) + (C
0
©
F)
(C
0
©
C
16
) + (C
0
©
Out)
(S
4
-S
0
©
C
16
) + (C
0
©
F)
(S
4
-S
0
©
C
16
) + (C
0
©
Out)
Same as 16-bit case
(C
0
©
C
16
) + (C
0
Setup time)
(S
4
-S
0
©
C
16
) + (C
0
Setup time)
Same as 16-bit case
(Clock
©
C
16
) + (C
0
Setup time)
A
31
-A
16
B
31
-B
16
A
15
-A
0
B
15
-B
0
D
Q
D
Q
D
Q
D
Q
CLOCK
C
0,
S
4
–S
0
A
F
B
C
0
A
C
16
16
F
B
C
0
MOST
SIGNIFICANT
SLICE
16
F
31
-F
16
F
15
-F
0
LEAST
SIGNIFICANT
SLICE
Arithmetic Logic Units
3
08/16/2000–LDS.383-E
LOGIC [ LOGIC DEVICES INCORPORATED ]
