L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
ALU STATUS
TABLE 2. ALU STATUS FLAGS
The ALU provides Overflow and Zero
status bits. Carry, Propagate, and
Generate outputs are also provided
for cascading. These outputs are
defined for the three arithmetic
functions only. The ALU sets the Zero
output when all 16 output bits are
zero. The Generate, Propagate, C16,
and OVF flags for the A + B operation
are defined in Table 2. The status
flags produced for NOT(A) + B and
A + NOT(B) can be found by comple-
menting Ai and Bi respectively in
Table 2.
Bit Carry Generate = gi=AiBi
Bit Carry Propagate = pi=Ai+ Bi
fori=0... 15
fori=0... 15
P0 = p0
Pi = pi(Pi–1)
fori=1... 15
and
G0 = g0
Gi = gi+pi(Gi–1)
C i = Gi–1 + Pi–1 (C0)
fori=1... 15
fori=1... 15
then
G = NOT(G15)
P = NOT(P15)
C16 = G15 + P15C0
OVF = C15 XOR C16
OPERAND REGISTERS
The L4C381 has two 16-bit wide in-
put registers for operands A and B.
These registers are rising edge trig-
gered by a common clock. The A
register is enabled for input by setting
the ENA control LOW, and the B
register is enabled for input by setting
the ENB control LOW. When either
the ENA control or ENB control is
HIGH, the data in the corresponding
input register will not change.
output register. By disabling the
output register, intermediate results
can be held while loading new input
operands. Three-state drivers con-
trolled by the OE input allow the
L4C381 to be configured in a single
bidirectional bus system.
TABLE 3. OPERAND SELECTION
OSB OSA OPERAND B OPERAND A
0
0
1
1
0
1
0
1
F
0
A
A
0
B
B
A
The output register can be bypassed
by asserting the FTF control signal
(FTF = HIGH). When the FTF control
is asserted, output data is routed
around the output register, however,
it continues to function normally via
the ENF control. The contents of the
output register will again be available
on the output pins if FTF is released.
With both FTAB and FTF true (HIGH)
the L4C381 is functionally identical to
four cascaded 54S381-type devices.
This architecture allows the L4C381 to
accept arguments from a single 16-bit
data bus. For those applications that
do not require registered inputs, both
the A and B operand registers can be
bypassed with the FTAB control line.
When the FTAB control is asserted
(FTAB = HIGH), data is routed
around the A and B input registers;
however, they continue to function
normally via the ENA and ENB
controls. The contents of the input
registers will again be available to the
ALU if the FTAB control is released.
When both operand select lines are
low, the L4C381 is configured as a
chain calculation ALU. The registered
ALU output is passed back to the B
input to the ALU. This allows accu-
mulation operations to be performed
by providing new operands via the A
input port. The accumulator can be
preloaded from the A input by setting
OSA true. By forcing the function
select lines to the CLEAR state (000),
the accumulator may be cleared. Note
that this feedback operation is not
OPERAND SELECTION
The two operand select lines, OSA and affected by the state of the FTF
OSB, control multiplexers that precede control. That is, the F outputs of the
OUTPUT REGISTER
the ALU inputs. These multiplexers
provide an operand force-to-zero
function as well as F register feedback function, however, and provides the
to the B input. Table 3 shows the
inputs to the ALU as a function of the
operand select inputs. Either the A or
B operands may be forced to zero.
L4C381 may be driven directly by the
ALU. The output register continues to
The output of the ALU drives the
input of a 16-bit register. This rising-
edge-triggered register is clocked by
the same clock as the input registers.
When the ENF control is LOW, data
from the ALU will be clocked into the
ALU B operand source.
Arithmetic Logic Units
08/16/2000–LDS.381-P
2
LOGIC [ LOGIC DEVICES INCORPORATED ]
