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L29C525JC15 参数 Datasheet PDF下载

L29C525JC15图片预览
型号: L29C525JC15
PDF下载: 下载PDF文件 查看货源
内容描述: 双管道注册 [Dual Pipeline Register]
分类和应用: 外围集成电路时钟
文件页数/大小: 6 页 / 173 K
品牌: LOGIC [ LOGIC DEVICES INCORPORATED ]
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L29C525
DEVICES INCORPORATED
Dual Pipeline Register
NOTES
1. Maximum Ratings indicate stress
specifications only. Functional oper-
ation of these products at values beyond
those indicated in the Operating Condi-
tions table is not implied. Exposure to
maximum rating conditions for ex-
tended periods may affect reliability.
9. AC specifications are tested with
input transition times less than 3 ns,
output reference levels of 1.5 V (except
t
DIS
test), and input levels of nominally
0 to 3.0 V. Output loading may be a
resistive divider which provides for
specified
I
OH
and
I
OL
at an output
voltage of
V
OH
min and
V
OL
max
respectively. Alternatively, a diode
bridge with upper and lower current
sources of
I
OH
and
I
OL
respectively,
and a balancing voltage of 1.5 V may be
used. Parasitic capacitance is 30 pF
minimum, and may be distributed.
11. For the
t
ENA
test, the transition is
measured to the 1.5 V crossing point
with datasheet loads. For the
t
DIS
test,
the transition is measured to the
±200mV level from the measured
steady-state output voltage with
±10mA loads. The balancing volt-
age, V
TH
, is set at 3.5 V for Z-to-0
and 0-to-Z tests, and set at 0 V for Z-
to-1 and 1-to-Z tests.
2. The products described by this spec-
ification include internal circuitry de-
signed to protect the chip from damag-
ing substrate injection currents and ac-
12. These parameters are only tested at
cumulations of static charge. Neverthe-
the high temperature extreme, which is
less, conventional precautions should
the worst case for leakage current.
be observed during storage, handling,
F
IGURE
A. O
UTPUT
L
OADING
C
IRCUIT
and use of these circuits in order to This device has high-speed outputs ca-
avoid exposure to excessive electrical pable of large instantaneous current
stress values.
pulses and fast turn-on/turn-off times.
S1
As a result, care must be exercised in the
3. This device provides hard clamping of testing of this device. The following
DUT
I
OL
transient undershoot and overshoot. In- measures are recommended:
V
TH
C
L
put levels below ground or above
V
CC
I
OH
will be clamped beginning at –0.6 V and a. A 0.1 µF ceramic capacitor should be
V
CC
+ 0.6 V. The device can withstand installed between
V
CC
and Ground
indefinite operation with inputs in the leads as close to the Device Under Test
F
IGURE
B. T
HRESHOLD
L
EVELS
range of –0.5 V to +7.0 V. Device opera- (DUT) as possible. Similar capacitors
t
ENA
t
DIS
tion will not be adversely affected, how- should be installed between device
V
CC
OE
1.5 V
1.5 V
ever, input current levels will be well in and the tester common, and device
ground and tester common.
excess of 100 mA.
3.5V Vth
0
Z
4. Actual test conditions may vary from b. Ground and
V
CC
supply planes
those designated but operation is guar- must be brought directly to the DUT
anteed as specified.
socket or contactor fingers.
5. Supply current for a given applica- c. Input voltages should be adjusted to
tion can be accurately approximated by: compensate for inductive ground and
V
CC
noise to maintain required DUT input
NCV
2
F
levels relative to the DUT ground pin.
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
6. Tested with all outputs changing ev- nal system must supply at least that
ery cycle and no load, at a 5 MHz clock much time to meet the worst-case re-
quirements of all parts. Responses from
rate.
the internal circuitry are specified from
7. Tested with all inputs within 0.1 V of the point of view of the device. Output
V
CC
or Ground, no load.
delay, for example, is specified as a
8. These parameters are guaranteed maximum since worst-case operation of
any device always provides data within
but not 100% tested.
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
1.5 V
V
OL
*
0.2 V
0
1
Z
Z
1.5 V
V
OH
*
0.2 V
Z
1
0V Vth
V
OL
* Measured V
OL
with I
OH
= –10mA and I
OL
= 10mA
V
OH
* Measured V
OH
with I
OH
= –10mA and I
OL
= 10mA
Pipeline Registers
5
03/32/2000–LDS.29C525-G