L10C11
DEVICES INCORPORATED
4/8-bit Variable Length Shift Register
NOTES
1. Maximum Ratings indicate stress 9. AC specifications are tested with
specifications only. Functional oper- input transition times less than 3 ns, measured to the 1.5 V crossing point
11. For the tENA test, the transition is
ation of these products at values be- output reference levels of 1.5 V (except
yond those indicated in the Operating
with datasheet loads. For the tDIS test,
the transition is m easu red to the
tDIS test), and input levels of nominally
Conditions table is not implied. Expo- 0 to 3.0 V. Output loading may be a ±200m V level from the m easu red
sure to maximum rating conditions for resistive divider which provides for steady-state ou tp u t voltage w ith
extended periods may affect reliability.
±10m A load s. The balancing volt-
age, VTH , is set at 3.5 V for Z-to-0
specified IOH and IOL at an output
voltage of VOH min and VOL max
2. The products described by this speci-
fication include internal circuitry de-
signedtoprotect the chipfrom damaging
substrate injection currents and accumu-
lations of static charge. Nevertheless,
conventional precautions should be ob-
served during storage, handling, and use
respectively. Alternatively, a diode and 0-to-Z tests, and set at 0 V for Z-
bridge with upper and lower current to-1 and 1-to-Z tests.
sources of IOH and IOL respectively,
12. These parameters are only tested at
and a balancing voltage of 1.5 V may be
the high temperature extreme, which is
used. Parasitic capacitance is 30 pF
the worst case for leakage current.
minimum, and may be distributed.
FIGURE A. OUTPUT LOADING CIRCUIT
of these circuits in order to avoid expo- This device has high-speed outputs ca-
sure to excessive electrical stress values. pable of large instantaneous current
pulses and fast turn-on/ turn-off times.
3. Thisdeviceprovideshard clamping of
As a result, care must be exercised in the
S1
DUT
transient undershoot and overshoot. In-
I
OL
testing of this device. The following
measures are recommended:
put levels below ground or above VCC
will be clamped beginning at –0.6 V and
V
TH
CL
I
OH
a. A 0.1 µF ceramic capacitor should be
VCC + 0.6 V. The device can withstand
indefinite operation with inputs in the
installed between VCC and Ground
range of –0.5 V to +7.0 V. Device opera- leads as close to the Device Under Test
tion will not be adversely affected, how- (DUT) as possible. Similar capacitors
FIGURE B. THRESHOLD LEVELS
t
ENA
tDIS
ever, input current levels will be well in
excess of 100 mA.
should be installed between device VCC
and the tester common, and device
ground and tester common.
OE
0
1.5 V
1.5 V
Z
Z
3.5V Vth
4. Actual test conditions may vary from
those designated but operation is guar-
anteed as specified.
1.5 V
1.5 V
V
OL*
0.2 V
0.2 V
0
1
Z
Z
b. Ground and VCC supply planes
must be brought directly to the DUT
socket or contactor fingers.
V
OH*
1
0V Vth
5. Supply current for a given application
can be accurately approximated by:
VOL* Measured VOL with IOH = –10mA and IOL = 10mA
VOH*
Measured VOH with IOH = –10mA and IOL = 10mA
c. Input voltages should be adjusted to
compensatefor inductiveground and VCC
noise to maintain required DUT input
levels relative to the DUT ground pin.
2
NCV F
4
where
10. Each parameter is shown as a min-
imum or maximum value. Input re-
quirements are specified from the point
of view of the external system driving
the chip. Setup time, for example, is
specified as a minimum since the exter-
nal system must supply at least that
much time to meet the worst-case re-
quirements ofall parts. Responses from
the internal circuitry are specified from
the point of view of the device. Output
delay, for example, is specified as a
maximum since worst-case operation of
any device always provides data within
that time.
N = total number of device outputs
C = capacitive load per output
V = supply voltage
F = clock frequency
6. Tested with all outputs changing ev-
ery cycle and no load, at a 5 MHz clock
rate.
7. Tested with all inputs within 0.1 V of
VCC or Ground, no load.
8. These parameters are guaranteed
but not 100% tested.
Pipeline Registers
03/27/2000–LDS.11-L
4
LOGIC [ LOGIC DEVICES INCORPORATED ]
