LT3975
TYPICAL PERFORMANCE CHARACTERISTICS
Load Transient: 0.5A to 2.5A
I
L
1A/DIV
I
L
1A/DIV
T
A
= 25°C, unless otherwise noted.
Load Transient: 20mA to 2A
V
OUT
200mV/DIV
12V
IN
3.3V
OUT
C
OUT
= 47µF
20µs/DIV
3975 G37
V
OUT
200mV/DIV
12V
IN
3.3V
OUT
C
OUT
= 47µF
20µs/DIV
3975 G38
PIN FUNCTIONS
FB (Pin 1):
The LT3975 regulates the FB pin to 1.197V.
Connect the feedback resistor divider tap to this pin. Also,
connect a phase lead capacitor between FB and the output.
Typically, this capacitor is 10pF
.
SS (Pin 2):
A capacitor is tied between SS and ground to
slowly ramp up the peak current limit of the LT3975 on
start-up. There is an internal 1.8μA pull-up on this pin.
The soft-start capacitor is actively discharged when the
EN pin goes low, during undervoltage lockout or thermal
shutdown. Float this pin to disable soft-start.
OUT (Pin 3):
This pin is an input to the dropout comparator
which maintains a minimum dropout of 500mV between
V
IN
and OUT. The OUT pin connects to the anode of the
internal boost diode. This pin also supplies the current to
the LT3975’s internal regulator when OUT is above 3.2V.
Connect this pin to the output when the programmed
output voltage is less than 16V.
BOOST (Pin 4):
This pin is used to provide a drive volt-
age, higher than the input voltage, to the internal bipolar
NPN power switch.
SW (Pins 5, 6, 7):
The SW pin is the output of an internal
power switch. Connect these pins to the inductor, catch
diode, and boost capacitor.
NC (Pins 8, 9):
No Connects. These pins are not connected
to internal circuitry.
V
IN
(Pins 10, 11, 12):
The V
IN
pin supplies current to the
LT3975’s internal circuitry and to the internal power switch.
These pins must be locally bypassed.
EN (Pin 13):
The part is in shutdown when this pin is low
and active when this pin is high. The hysteretic threshold
voltage is 1.08V going up and 1.02V going down. The
EN threshold is only accurate when V
IN
is above 4.3V. If
V
IN
is lower than 3.9V, internal UVLO will place the part
in shutdown. Tie to V
IN
if shutdown feature is not used.
RT (Pin 14):
A resistor is tied between RT and ground to
set the switching frequency.
PG (Pin 15):
The PG pin is the open-drain output of an
internal comparator. PGOOD remains low until the FB pin
is within 8.4% of the final regulation voltage. PGOOD is
valid when V
IN
is above 2V.
SYNC (Pin 16):
This is the external clock synchronization
input. Ground this pin for low ripple Burst Mode operation
at low output loads. Tie to a clock source for synchroni-
zation, which will include pulse skipping at low output
loads. When in pulse-skipping mode, quiescent current
increases to 11µA in a typical application at no load. Do
not float this pin.
GND (Exposed Pad Pin 17):
Ground. The exposed pad
must be soldered to the PCB.
3975f
8
LINER [ LINEAR TECHNOLOGY ]
