LTC3400/LTC3400B
OPERATIO
burst threshold, the LTC3400 will resume continuous
PWM operation seamlessly. Referring to the Block Dia-
gram, an optional capacitor (C
FF
) between V
OUT
and FB in
some circumstances can reduce the peak-to-peak V
OUT
ripple and input quiescent current during Burst Mode
APPLICATIO S I FOR ATIO
PCB LAYOUT GUIDELINES
The high speed operation of the LTC3400/LTC3400B
demands careful attention to board layout. You will not get
advertised performance with careless layout. Figure 2
shows the recommended component placement. A large
ground pin copper area will help to lower the chip tempera-
ture. A multilayer board with a separate ground plane is
ideal, but not absolutely necessary.
(OPTIONAL)
OUTPUT CURRENT (mA)
V
IN
1
2
3
SW
V
IN
6
GND V
OUT
5
FB SHDN 4
SHDN
V
OUT
3400 F02
RECOMMENDED COMPONENT PLACEMENT. TRACES
CARRYING HIGH CURRENT ARE DIRECT. TRACE AREA AT
FB PIN IS SMALL. LEAD LENGTH TO BATTERY IS SHORT
Figure 2. Recommended Component Placement
for Single Layer Board
COMPONENT SELECTION
Inductor Selection
The LTC3400/LTC3400B can utilize small surface mount
and chip inductors due to their fast 1.2MHz switching
frequency. A minimum inductance value of 3.3µH is
necessary for 3.6V and lower voltage applications and
4.7µH for output voltages greater than 3.6V. Larger values
6
U
W
U U
U
operation. Typical values for C
FF
range from 15pF to
220pF. The LTC3400B does not use Burst Mode operation
and features continous operation at light loads, eliminat-
ing low frequency output voltage ripple at the expense of
light load efficiency.
of inductance will allow greater output current capability
by reducing the inductor ripple current. Increasing the
inductance above 10µH will increase size while providing
little improvement in output current capability.
The approximate output current capability of the LTC3400/
LTC3400B versus inductance value is given in the equa-
tion below and illustrated graphically in Figure 3.
180
160
140
120
V
OUT
= 5V
110
80
60
3
5
7
9 11 13 15 17 19 21 23
INDUCTANCE (µH)
3400 F03
V
IN
=1.2V
V
OUT
= 3V
V
OUT
= 3.3V
V
OUT
= 3.6V
Figure 3. Maximum Output Current vs
Inductance Based On 90% Efficiency
V •D
I
OUT(MAX)
= η
•
I
P
–
IN
•
(
1 – D
)
f • L • 2
where:
η
= estimated efficiency
I
P
= peak current limit value (0.6A)
V
IN
= input (battery) voltage
D = steady-state duty ratio = (V
OUT
– V
IN
)/V
OUT
f = switching frequency (1.2MHz typical)
L = inductance value
3400fa
LINER [ LINEAR TECHNOLOGY ]
