LTC1629/LTC1629-PG
U
W U U
APPLICATIO S I FOR ATIO
The worst-case power disipated by the synchronous
MOSFET under short-circuit conditions at elevated ambi-
ent temperature and estimated 50°C junction temperature
rise is:
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1629. These items are also illustrated graphically in
the layout diagram of Figure 11. Check the following in
your layout:
2
5.5V − 1.8V
PSYNC
=
5.28A 1.48 0.013Ω
(
) (
)(
)
5.5V
= 360mW
1) Are the signal and power grounds segregated? The
LTC1629 signal ground pin should return to the (–) plate
of COUT separately. The power ground returns to the
sources of the bottom N-channel MOSFETs, anodes of the
Schottky diodes, and (–) plates of CIN, which should have
as short lead lengths as possible.
which is much less than normal, full-load conditions.
Incidentally, since the load no longer dissipates power in
the shorted condition, total system power dissipation is
decreased by over 99%.
2) Does the LTC1629 VOS+ pin connect to the (+) plate(s)
of COUT? Does the LTC1629 VOS– pin connect to the (–)
plate(s) of COUT? The resistive divider R1, R2 must be
connected between the VDIFFOUT and signal ground and
anyfeedforwardcapacitoracrossR1shouldbeascloseas
possible to the LTC1629.
3)AretheSENSE– andSENSE+ leadsroutedtogetherwith
minimum PC trace spacing? The filter capacitors between
SENSE+ and SENSE– pin pairs should be as close as
possible to the LTC1629. Ensure accurate current sensing
with Kelvin connections to the sense resistors.
The duty cycles when the peak RMS input current occurs
is at D = 0.25 and D = 0.75 according to Figure 4. Calculate
the worst-case required RMS input current rating at the
input voltage, which is 5.5V, that provides a duty cycle
nearest to the peak.
From Figure 4, CIN will require an RMS current rating of:
CINrequiredIRMS = 20A 0.23
(
)(
)
= 4.6ARMS
The output capacitor ripple current is calculated by using
the inductor ripple already calculated for each inductor
andmultiplyingbythefactorobtainedfromFigure 3along
with the calculated duty factor. The output ripple in con-
tinuous mode will be highest at the maximum input
voltage.FromFigure3,themaximumoutputcurrentripple
is:
4) Do the (+) plates of CIN connect to the drains of the
topside MOSFETs as closely as possible? This capacitor
provides the AC current to the MOSFETs. Keep the input
currentpathformedbytheinputcapacitor,topandbottom
MOSFETs, and the Schottky diode on the same side of the
PC board in a tight loop to minimize conducted and
radiated EMI.
VOUT
fL
∆ICOUT
=
0.34
(
)
5) Is the INTVCC 1µF ceramic decoupling capacitor con-
nectedcloselybetweenINTVCC andthepowergroundpin?
This capacitor carries the MOSFET driver peak currents. A
small value is used to allow placement immediately adja-
cent to the IC.
1.8 0.34
300kHz 2µH
)(
(
)
∆ICOUTMAX
=
= 1A
(
)
Note that the PolyPhase technique will have its maximum
benefit for input and output ripple currents when the
number of phases times the output voltage is approxi-
mately equal to or greater than the input voltage.
6) Keep the switching nodes, SW1 (SW2), away from
sensitive small-signal nodes. Ideally the switch nodes
should be placed at the furthest point from the LTC1629.
7)Usealowimpedancesourcesuchasalogicgatetodrive
the PLLIN pin and keep the lead as short as possible.
23
Linear [ Linear ]
