LTC1450/LTC1450L
U
DIGITAL INTERFACE TRUTH TABLE
H
H
H
H
H
H
H
H
H
H
L
H
H
H
L
L
↑
L
L
↑
L
↑
L
L
↑
L
H
H
L
L
X
H
H
H
H
H
H
L
Loads the eight LSBs into the input latch
Latches the eight LSBs into the input latch
Latches the eight LSBs into the input latch
Loads the four MSBs into the input latch
Latches the four MSBs into the input latch
Latches the four MSBs into the input latch
Loads the input latch data into the DAC latch
Latches the input latch data into the DAC latch
Loads input data into DAC latches (latches transparent)
Latches input data into DAC latches
H
H
H
H
H
L
H
H
L
L
X
↑
L
↑
L
X
X
All zeros loaded into input and DAC latches
W U
W
TIMING DIAGRAM
t
CS
CSLSB
t
CS
CSMSB
t
t
t
t
WR
CWH
DWH
CWS
t
WR
WR
t
LDAC
LDAC
t
DWS
DAC UPDATE
DATA VALID
DATA VALID
DATA
LTC1450/50L • TD01
W
BLOCK DIAGRAM
20
19
18
17
22
V
REFOUT
REFHI REFLO X1/X 2
CC
–
+
V
OUT 21
REFERENCE
LTC1450: 2.048V
LTC1450L: 1.22V
DAC
16
GND
24 LDAC
12-BIT DAC LATCH
23 CLR
POWER-ON
RESET
CSMSB
3
UPPER 4-BIT
INPUT LATCH
LOWER 8-BIT
INPUT LATCH
1
2
WR
CSLSB
D11
(MSB) D10 D9 D8
D0
D7 D6 D5 D4 D3 D2 D1 (LSB)
15 14 13 12
11 10
9
8
7
6
5
4
LTC1450/50L • BD
8
Linear [ Linear ]
