LTC1450/LTC1450L
U
U
U
PIN FUNCTIONS
Write Input (Active Low). Used with CSMSB
and/orCSLSBtoloaddataintotheinputlatches.WhileWR
and CSMSB and/or CSLSB are held low the enabled input
latches are transparent. The rising edge of WR will latch
data into all input latches.
An input code of (000H) will connect the positive input of
the output buffer to this end. Can be used to offset the zero
scale above ground.
Upper input terminal of the DAC’s internal
resistor string. Typically connected to REFOUT. An input
code of (FFFH) will connect the positive input of the output
buffer to 1LSB from this end.
Chip Select Least Significant Byte (Active
Low). Used with WR to load data into the eight LSB input
latches. While WR and CSLSB are held low the eight LSB
input latches are transparent. The rising edge will latch
data into the eight LSB input latches. Can be connected to
CSMSB for simultaneous loading of both sets of input
latches on a 12-bit bus.
Output of the internal 2.048V/1.22V
reference. Typically connected to REFHI to drive internal
DAC resistor string.
Positive Power Supply Input. 4.5V ≤ VCC
≤
5.5V (LTC1450) and 2.7V ≤ VCC ≤ 5.5V (LTC1450L).
Requires a bypass capacitor to ground.
Chip Select Most Significant Byte (Active
Low). Used with WR to load data into the four MSB input
latches. While WR and CSMSB are held low the four MSB
input latches are transparent. The rising edge will latch
data into the four MSB input latches. Can be connected to
CSLSB for simultaneous loading of both sets of input
latches on a 12-bit bus.
Buffered DAC Output.
GainSettingResistorPin. ConnecttoGND
for G = 2 or to VOUT for G = 1. Should always be tied to a
low impedance source, such as ground or VOUT, to ensure
stabilityoftheoutputbufferwhendrivingcapacitiveloads.
InputdatafortheLeastSignificant
Byte. Loaded into LSB input latch when WR = 0 and
CSLSB = 0.
Clear Input (Asynchronous Active Low). A
low on this pin asynchronously resets all internal latches
to 0s.
Input data for the
Most Significant Byte. Loaded into MSB input latch when
WR = 0 and CSMSB = 0. Can be connected to D0 to D3 for
multiplexed operation on an 8-bit bus.
Load DAC (Asynchronous Active Low).
Used to asynchronously transfer the contents of the input
latches to the DAC latches which updates the output
voltage. The rising edge latches the data into the DAC
latches. If held low the DAC latches are transparent and
Ground.
data from the input latches will immediately update VOUT
.
Lower input terminal of the DAC’s inter-
nal resistor string. Typically connected to Analog Ground.
7
Linear [ Linear ]
