LT3580
APPLICATIONS INFORMATION
provided to a load (I
OUT
). In order to provide adequate
load current, L should be at least:
DC • V
IN
L
>
⎛
|V |• I
⎞
2(f)
⎜
I
LIM
−
OUT OUT
⎟
V
IN
•
η ⎠
⎝
for boost, topologies, or:
L
>
⎛
2(f)
⎜
I
LIM
−
⎜
⎝
DC • V
IN
V
OUT
• I
OUT
V
IN
•
η
⎞
−
I
OUT
⎟
⎟
⎠
for the uncoupled inductor SEPIC and uncoupled inductor
inverting topologies.
Maximum Inductance:
Excessive inductance can reduce
current ripple to levels that are difficult for the current com-
parator (A3 in the Block Diagram) to cleanly discriminate,
thus causing duty cycle jitter and/or poor regulation. The
maximum inductance can be calculated by:
L
MAX
=
V
IN
– V
CESAT
DC
•
I
MIN−RIPPLE
f
for the SEPIC and inverting topologies.
where:
L = L1||L2 for uncoupled dual inductor topologies
DC = switch duty cycle (see previous section)
I
LIM
= switch current limit, typically about 2.4A at 50%
duty cycle (see the Typical Performance Characteristics
section).
η
= power conversion efficiency (typically 88% for
boost and 75% for dual inductor topologies at high
currents).
f = switching frequency
Negative values of L indicate that the output load current
I
OUT
exceeds the switch current limit capability of the
LT3580.
where L
MAX
is L1||L2 for uncoupled dual inductor topolo-
gies and I
MIN-RIPPLE
is typically 95mA.
Current Rating:
Finally, the inductor(s) must have a rating
greater than its peak operating current to prevent inductor
saturation resulting in efficiency loss. In steady state, the
peak input inductor current (continuous conduction mode
only) is given by:
I
L1−PEAK
=
V
OUT
•I
OUT
V
IN
•
η
+
V
IN
• DC
2 • L1• f
for the boost, uncoupled inductor SEPIC and uncoupled
inductor inverting topologies.
For uncoupled dual inductor topologies, the peak output
inductor current is given by:
I
L2−PEAK
=I
OUT
+
V
OUT
•
(
1– DC
)
2 • L2 • f
Avoiding Subharmonic Oscillations:
The LT3580’s internal
slope compensation circuit will prevent subharmonic oscil-
lations that can occur when the duty cycle is greater than
50%, provided that the inductance exceeds a minimum
value. In applications that operate with duty cycles greater
than 50%, the inductance must be at least:
V •
(
2 • DC – 1
)
L
>
IN
(1−DC) • (f)
for boost, coupled inductor SEPIC, and coupled inductor
inverting topologies, or:
L1 L2
>
V
IN
•
(
2 • DC – 1
)
(1−DC) • (f)
For the coupled inductor topologies:
⎡
V
OUT
⎤
V
IN
• DC
I
OUT
⎢
1+
⎥+
⎣ η•
V
IN
⎦
2 • L • f
Note: Inductor current can be higher during load transients.
It can also be higher during start-up if inadequate soft-start
capacitance is used.
Capacitor Selection
Low ESR (equivalent series resistance) capacitors should
be used at the output to minimize the output ripple voltage.
Multilayer ceramic capacitors are an excellent choice, as
they have an extremely low ESR and are available in very
small packages. X5R or X7R dielectrics are preferred, as
3580fg
9
LINER [ LINEAR TECHNOLOGY ]
