LT1763 Series
U
W U U
APPLICATIONS INFORMATION
plus the ADJ pin bias current. The ADJ pin bias current,
30nA at 25°C, flows through R2 into the ADJ pin. The
output voltage can be calculated using the formula in
Figure 2. The value of R1 should be no greater than 250k
to minimize errors in the output voltage caused by the ADJ
pinbiascurrent.Notethatinshutdowntheoutputisturned
off and the divider current will be zero. Curves of ADJ Pin
Voltage vs Temperature and ADJ Pin Bias Current vs
Temperature appear in the Typical Performance Charac-
teristics section.
10µs, with total output voltage deviation of less than 2.5%
(see LT1763-5 Transient Response in the Typical Perfor-
mance Characteristics). However, regulator start-up time
is inversely proportional to the size of the bypass capaci-
tor, slowing to 15ms with a 0.01µF bypass capacitor and
10µF output capacitor.
Output Capacitance and Transient Response
The LT1763 regulators are designed to be stable with a
wide range of output capacitors. The ESR of the output
capacitor affects stability, most notably with small capaci-
tors. A minimum output capacitor of 3.3µF with an ESR of
3Ω or less is recommended to prevent oscillations. The
LT1763-X is a micropower device and output transient
response will be a function of output capacitance. Larger
values of output capacitance decrease the peak deviations
and provide improved transient response for larger load
current changes. Bypass capacitors, used to decouple
individual components powered by the LT1763-X, will
increase the effective output capacitor value. With larger
capacitors used to bypass the reference (for low noise
operation), larger values of output capacitors are needed.
For 100pF of bypass capacitance, 4.7µF of output capaci-
tor is recommended. With a 1000pF bypass capacitor or
larger, a 6.8µF output capacitor is recommended.
IN
OUT
V
OUT
+
V
IN
R2
LT1763
GND
R2
R1
VOUT = 1.22V 1+
ADJ = 1.22V
ADJ = 30nA AT 25°C
OUTPUT RANGE = 1.22V TO 20V
+ I
R2
(
ADJ)(
)
ADJ
V
R1
I
1763 F02
Figure 2. Adjustable Operation
The adjustable device is tested and specified with the ADJ
pin tied to the OUT pin for an output voltage of 1.22V.
Specifications for output voltages greater than 1.22V will
beproportionalto the ratio ofthe desired outputvoltage to
1.22V: VOUT/1.22V. For example, load regulation for an
output current change of 1mA to 500mA is –2mV typical
at VOUT = 1.22V. At VOUT = 12V, load regulation is:
TheshadedregionofFigure3definestherangeoverwhich
the LT1763 regulators are stable. The minimum ESR
needed is defined by the amount of bypass capacitance
used, while the maximum ESR is 3Ω.
(12V/1.22V)(–2mV) = –19.6mV
Bypass Capacitance and Low Noise Performance
The LT1763 regulators may be used with the addition of a
bypass capacitor from VOUT to the BYP pin to lower output
voltage noise. A good quality low leakage capacitor is
recommended. This capacitor will bypass the reference of
the regulator, providing a low frequency noise pole. The
noise pole provided by this bypass capacitor will lower the
output voltage noise to as low as 20µVRMS with the
addition of a 0.01µF bypass capacitor. Using a bypass
capacitor has the added benefit of improving transient
response. With no bypass capacitor and a 10µF output
capacitor, a 10mA to 500mA load step will settle to within
1% of its final value in less than 100µs. With the addition
of a 0.01µF bypass capacitor, the output will settle to
within 1% for a 10mA to 500mA load step in less than
4.0
3.5
3.0
STABLE REGION
2.5
2.0
C
= 0
BYP
1.5
1.0
0.5
0
C
= 100pF
BYP
C
= 330pF
BYP
C
≥ 1000pF
BYP
1
3
6
9 10
7 8
2
4
5
OUTPUT CAPACITANCE (µF)
1763 F03
Figure 3. Stability
1763fa
12
Linear [ Linear ]
