LT1372/LT1377
W U U
U
APPLICATIO S I FOR ATIO
Frequency Compensation
(magnetic) radiation is minimized by keeping output di-
ode, switch pin, and output bypass capacitor leads as
short as possible. E field radiation is kept low by minimiz-
ingthelengthandareaofalltracesconnectedtotheswitch
pin. A ground plane should always be used under the
switcher circuitry to prevent interplane coupling.
Loopfrequencycompensationisperformedontheoutput
of the error amplifier (VC pin) with a series RC network.
The main pole is formed by the series capacitor and the
output impedance (≈500kΩ) of the error amplifier. The
pole falls in the range of 2Hz to 20Hz. The series resistor
creates a “zero” at 1kHz to 5kHz, which improves loop
stability and transient response. A second capacitor,
typically one-tenth the size of the main compensation
capacitor, is sometimes used to reduce the switching
frequency ripple on the VC pin. VC pin ripple is caused by
output voltage ripple attenuated by the output divider and
multiplied by the error amplifier. Without the second
capacitor, VC pin ripple is:
Thehighspeedswitchingcurrentpathisshownschemati-
cally in Figure 3. Minimum lead length in this path is
essential to ensure clean switching and low EMI. The path
including the switch, output diode, and output capacitor is
the only one containing nanosecond rise and fall times.
Keep this path as short as possible.
SWITCH
NODE
L1
V
OUT
1.245(V
)(g )(R )
m C
RIPPLE
(V
HIGH
FREQUENCY
CIRCULATING
PATH
V Pin Ripple =
C
V
IN
LOAD
)
OUT
V
m
= Output ripple (V
)
P–P
RIPPLE
g = Error amplifier transconductance
(≈1500µmho)
LT1372 • F03
Figure 3
R = Series resistor on V pin
V
C
OUT
C
= DC output voltage
More Help
To prevent irregular switching, VC pin ripple should be For more detailed information on switching regulator
kept below 50mVP–P. Worst-case VC pin ripple occurs at circuits, please see Application Note 19. Linear Technol-
maximum output load current and will also be increased ogyalsooffersacomputersoftwareprogram,SwitcherCAD,
if poor quality (high ESR) output capacitors are used. The to assist in designing switching converters. In addition,
addition of a 0.0047µF capacitor on the VC pin reduces our applications department is always ready to lend a
switching frequency ripple to only a few millivolts. A low helping hand.
value for RC will also reduce VC pin ripple, but loop phase
margin may be inadequate.
Switch Node Considerations
For maximum efficiency, switch rise and fall time are
made as short as possible. To prevent radiation and high
frequency resonance problems, proper layout of the com-
ponents connected to the switch node is essential. B field
10
Linear [ Linear ]
