LT1175
U
W
U U
APPLICATIONS INFORMATION
To estimate regulator output ripple under different condi-
tions, the following general comments should be helpful:
to save space. At heavier loads an inductor may have to be
used in place of the resistor. The value of the inductor can
be calculated from:
1. Output ripple at high frequency is only weakly affected
by load current or output capacitor size for medium to
heavy loads. At very light loads (<10mA), higher fre-
quency ripple may be reduced by using larger output
capacitors.
ESR
L
=
FIL
rr / 20
10
2π f
( )
ESR = Effective series resistance of filter capacitor. This
assumes that the capacitive reactance is small
compared to ESR, a reasonable assumption for
solid tantalum capacitors above 2.2µF and 50kHz.
2. A feedforward capacitor across the resistor divider
used with the adjustable part is effective in reducing
rippleonlyforoutputvoltages greaterthan5Vandonly
for frequencies less than 100kHz.
f
= Ripple frequency
3. Input-to-output voltage differential has little effect on
ripple rejection until the regulator actually enters a
dropout condition of 0.2V to 0.6V.
rr = Ripple rejection ratio of filter in dB
Example: ESR = 1.2Ω, f = 100kHz, rr = –25dB.
If ripple rejection needs to be improved, an input filter can
be added. This filter can be a simple RC filter using a 1Ω
to 10Ω resistor. A 3.3Ω resistor for instance, combined
with a 0.3Ω ESR solid tantalum capacitor, will give an
additional 20dB ripple rejection. The size of the resistor
will be dictated by maximum load current. If the maximum
voltage drop allowable across the resistor is “VR,” and
maximum load current is ILOAD, R = VR/ILOAD. At light
loads, larger resistors and smaller capacitors can be used
1.2
L
=
= 34µH
FIL
5
−25/ 20
10
6.3 10
Solid tantalum capacitors are suggested for the filter to
keep filter Q fairly low. This prevents unwanted ringing at
the resonant frequency of the filter and oscillation prob-
lems with the filter/regulator combination.
U
PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted.
Q Package
5-Lead Plastic DD Pak
(LTC DWG # 05-08-1461)
0.060
0.390 – 0.415
(9.906 – 10.541)
(1.524)
TYP
0.060
(1.524)
0.165 – 0.180
(4.191 – 4.572)
0.256
(6.502)
0.045 – 0.055
(1.143 – 1.397)
15° TYP
+0.008
0.004
–0.004
0.060
(1.524)
0.183
(4.648)
0.059
(1.499)
TYP
0.330 – 0.370
(8.382 – 9.398)
+0.203
0.102
(
)
–0.102
0.095 – 0.115
(2.413 – 2.921)
0.075
(1.905)
0.057 – 0.077
(1.447 – 1.955)
0.050 ± 0.012
(1.270 ± 0.305)
0.300
(7.620)
0.013 – 0.023
(0.330 – 0.584)
+0.012
0.143
–0.020
0.028 – 0.038
(0.711 – 0.965)
+0.305
3.632
BOTTOM VIEW OF DD PAK
HATCHED AREA IS SOLDER PLATED
COPPER HEAT SINK
(
)
–0.508
Q(DD5) 0396
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofits circuits as describedhereinwillnotinfringeonexistingpatentrights.
11
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