LT1016
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
+
= 5V, V
–
= 5V, V
OUT
(Q) = 1.4V, V
LATCH
= 0V, unless otherwise noted.
SYMBOL
V
OS
∆V
OS
/∆T
I
OS
I
B
PARAMETER
Input Offset Voltage
Input Offset Voltage Drift
Input Offset Current
Input Bias Current
Input Voltage Range
CMRR
PSRR
Common Mode Rejection
Supply Voltage Rejection
(Note 2)
●
ELECTRICAL CHARACTERISTICS
CONDITIONS
R
S
≤ 100Ω (Note 2)
●
●
MIN
LT1016C/I
TYP
1.0
4
0.3
0.3
5
MAX
±3
3.5
1.0
1.3
10
13
3.5
3.5
UNITS
mV
mV
µV/°C
µA
µA
µA
µA
V
V
dB
dB
dB
dB
V/V
V
V
(Note 3)
●
(Note 6)
Single 5V Supply
–3.75V ≤ V
CM
≤ 3.5V
Positive Supply 4.6V ≤ V
+
≤ 5.4V
LT1016C
Positive Supply 4.6V ≤ V
+
≤ 5.4V
LT1016I
Negative Supply 2V ≤ V
–
≤ 7V
●
●
●
●
●
●
–3.75
1.25
80
60
54
80
1400
2.7
2.4
96
75
75
100
3000
3.4
3.0
0.3
0.4
25
3
2.0
A
V
V
OH
V
OL
I
+
I
–
V
IH
V
IL
I
IL
t
PD
Small-Signal Voltage Gain
Output High Voltage
Output Low Voltage
Positive Supply Current
Negative Supply Current
LATCH Pin Hi Input Voltage
LATCH Pin Lo Input Voltage
LATCH Pin Current
Propagation Delay (Note 4)
1V ≤ V
OUT
≤ 2V
V
+
≥ 4.6V
I
OUT
=1mA
I
OUT
= 10mA
I
SINK
= 4mA
I
SINK
= 10mA
●
●
●
●
●
●
●
0.5
35
5
0.8
500
V
V
mA
mA
V
V
µA
ns
ns
ns
ns
ns
ns
V
LATCH
= 0V
∆V
IN
= 100mV, OD = 5mV
∆V
IN
= 100mV, OD = 20mV
●
10
●
14
16
12
15
3
9
●
∆t
PD
Differential Propagation Delay
Latch Setup Time
(Note 4) ∆V
IN
= 100mV,
OD = 5mV
2
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
Input offset voltage is defined as the average of the two voltages
measured by forcing first one output, then the other to 1.4V. Input offset
current is defined in the same way.
Note 3:
Input bias current (I
B
) is defined as the average of the two input
currents.
Note 4:
t
PD
and ∆t
PD
cannot be measured in automatic handling equipment
with low values of overdrive. The LT1016 is sample tested with a 1V step
and 500mV overdrive. Correlation tests have shown that t
PD
and ∆t
PD
limits shown can be guaranteed with this test if additional DC tests are
performed to guarantee that all internal bias conditions are correct. For low
overdrive conditions V
OS
is added to overdrive. Differential propogation
delay is defined as: ∆t
PD
= t
PDLH
– t
PDHL
Note 5:
Electrical specifications apply only up to 5.4V.
Note 6:
Input voltage range is guaranteed in part by CMRR testing and
in part by design and characterization. See text for discussion of input
voltage range for supplies other than ±5V or 5V.
Note 7:
This parameter is guaranteed to meet specified performance
through design and characterization. It has not been tested.
Rev D
For more information
3
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