LTC2641/LTC2642
BLOCK DIAGRAMS
LTC±641
LTC±64±
7
1
9
1
REF
REF
V
V
DD
DD
R
FB
8
7
LTC2641-16
LTC2641-14
LTC2641-12
LTC2642-16
LTC2642-14
LTC2642-12
INV
V
OUT
V
OUT
POWER-ON
RESET
POWER-ON
RESET
16-/14-/12-BIT DAC
6
16-/14-/12-BIT DAC
6
CS
CS
2
3
4
5
2
3
4
5
SCLK
DIN
CLR
SCLK
DIN
CLR
CONTROL
LOGIC
CONTROL
LOGIC
16-BIT DATA LATCH
16-BIT DATA LATCH
16-BIT SHIFT REGISTER
16-BIT SHIFT REGISTER
GND
8
GND
10
2641 BD
2642 BD
TIMING DIAGRAM
t
1
t
t
t
t
6
2
3
4
1
2
3
15
16
SCK
SDI
t
8
t
5
t
7
26412 TD
CS/LD
OPERATION
General Description
Digital-to-Analog Architecture
The DAC architecture is a voltage switching mode resis-
tor ladder using precision thin-film resistors and CMOꢀ
switches. TheLTC2641/LTC2642DACresistorladdersare
composed of a proprietary arrangement of matched DAC
sections. The four MꢀSs are decoded to drive 15 equally
weighted segments, and the remaining lower bits drive
successively lower weighted sections. Major carry glitch
The LTC2641/LTC2642 family of 16-/14-/12-bit voltage
output DACs offer full 16-bit performance with less than
2LꢀSintegrallinearityerrorandlessthan 1LꢀSdifferen-
tiallinearityerror,guaranteeingmonotonicoperation.They
operate from a single supply ranging from 2.7V to 5.5V,
consuming 120μA (typicalN. An external voltage reference
of 2V to V determines the DAC’s full-scale output volt-
DD
impulse is very low at 500pV•sec, C = 10pF, ten times
age.A3-wireserialinterfaceallowstheLTC2641/LTC2642
to fit into a small 8-/10-pin MꢀOP or DFI 3mm × 3mm
package.
L
lower than previous DACs of this type.
26412f
10
Linear [ Linear ]
