LTC2641/LTC2642
OPERATION
The digital-to-analog transfer function at the V
is:
⎯
⎯
pin
chip select input (CꢀN controls and frames the loading
OUT
⎯
⎯
of serial data from the data input (DꢁIN. Following a Cꢀ
high-to-low transition, the data on DꢁI is loaded, MꢀS
first, into the shift register on each rising edge of the serial
clock input (ꢀCLKN. After 16 data bits have been loaded
intotheserialinputregister, alow-to-hightransitiononCꢀ
transfersthedatatothe16-bitDAClatch,updatingtheDAC
output (see Figures 1a, 1b, 1cN. While Cꢀ remains high,
the serial input shift register is disabled. ꢁf there are less
than16low-to-hightransitionsonꢀCLKwhileCꢀremains
low, the data will be corrupted, and must be reloaded.
Also, if there are more than 16 low-to-high transitions
on ꢀCLK while Cꢀ remains low, only the last 16 data bits
loaded from DꢁI will be transferred to the DAC latch. For
the 14-bit DACs, (LTC2641-14/LTC2642-14N, the MꢀS
remains in the same (left-justifiedN position in the input
16-bit data word. Therefore, two “don’t-care” bits must
be loaded after the LꢀS, to make up the required 16 data
bits (Figure 1bN. ꢀimilarly, for the 12-bit family members
(LTC2641-12/LTC2642-12N four “don’t-care” bits must
follow the LꢀS (Figure 1cN.
k
⎛
⎞
⎠
VOUT(IDEAL)
=
V
⎜
⎝
N⎟ REF
2
⎯
⎯
where k is the decimal equivalent of the binary DAC input
code, I is the resolution, and V is between 2.0V and
REF
⎯
⎯
V
(see Tables 1a, 1b and 1cN.
DD
The LTC2642 includes matched resistors that are tied to
an external amplifier to provide bipolar output swing (Fig-
ure 2N. The bipolar transfer function at the RFS pin is:
⎯
⎯
⎯
⎯
k
N–1
⎛
⎞
⎠
VOUT _BIPOLAR(IDEAL) = VREF ⎜
– 1
⎟
⎝
2
(see Tables 2a, 2b and 2cN.
ꢀerial Interface
The LTC2641/LTC2642 communicates via a standard
3-wire ꢀPꢁ/QꢀPꢁ/MꢁCROWꢁRE compatible interface. The
CS
DAC
UPDATED
SCLK
DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
26412 F01a
DATA (16 BITS)
Figure 1a. 16-Bit Timing Diagram (LTC±641-16/LTC±64±-16)
CS
DAC
UPDATED
SCLK
DIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
X
X
26412 F01b
DATA (14 BITS + 2 DON’T-CARE BITS)
Figure 1b. 14-Bit Timing Diagram (LTC±641-14/LTC±64±-14)
CS
SCLK
DIN
DAC
UPDATED
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
X
X
X
X
26412 F01c
DATA (12 BITS + 4 DON’T-CARE BITS)
Figure 1c. 1±-Bit Timing Diagram (LTC±641-1±/LTC±64±-1±)
26412f
11
Linear [ Linear ]
