LTC1052/LTC7652
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Response Time vs Overdrive
VREF + OVERDRIVE
INPUT
{
VREF – 1mV
10µV
5V
50µV
5µV
OUTPUT
{
–5V
20ms/DIV
TEST CIRCUITS
Electrical Characteristics Test Circuit (TC1)
DC to 10Hz and DC to 1HZ Noise Test Circuit (TC3)
C2
C3
R2
1M
R2
R4
R1
1k
+
3
2
V
+
–
2
3
7
+
6
V
OUTPUT
(NOISE x 20,000)
–
C4
LT1001
34k
2
3
R3
6
7
OUTPUT
–
LTC1052
6
8
+
LTC1052
R1
R
4
L
8
1
+
4
1
0.1µF
0.1µF
34k
0.1µF
0.1µF
–
V
–
LTC1052/7652 • TC01
V
BANDWIDTH
10Hz
R1
16.2Ω
16.2Ω
R2
162k
162k
R3
16.2k
162k
R4
16.2k
162k
C2
0.1µF
1.0µF
C3
1.0µF
1.0µF
C4
1.0µF
1.0µF
1Hz
LTC1052/7652 • TC02
U
THEORY OF OPERATIO
DC OPERATION
The shaded portion of the LTC1052 block diagram
(Figure 1a) entirely determines the amplifier’s DC
characteristics. During the auto zero portion of the cycle,
the gm1 inputs are shorted together and a feedback path is
closed around the input stage to null its offset. Switch S2
and capacitor CEXTA act as a sample-and-hold to store the
nulling voltage during the next step—the sampling cycle.
stage. CEXTB and S2 act as a sample-and-hold to store the
amplified input signal during the auto zero cycle.
By switching between these two states at a frequency
much higher than the signal frequency, a continuous
output results.
Notice that during the auto zero cycle the gm1 inputs are
not only shorted together, but are also shorted to the
invertinginput.Thisforcesnullingwiththecommonmode
voltage present and accounts for the extremely high
In the sampling cycle, the zeroed amplifier is used to
amplify the differential input voltage. Switch S2 connects
the amplified input voltage to CEXTB and the output gain
CMRR of the LTC1052. In the same fashion, variations in
1052fa
6
Linear [ Linear ]
