LT1931/LT1931A
W
BLOCK DIAGRA
V
V
IN
5
IN
R5
80k
R6
80k
1
SW
+
–
COMPARATOR
A2
–
+
A1
m
DRIVER
g
LATCH
S
Q3
R
Q
R
C
RAMP
Q1
Q2
Σ
GENERATOR
x10
C
+
–
C
V
OUT
R3
30k
0.01Ω
1.2MHz
OSCILLATOR
R1
C
PL
(EXTERNAL)
R4
150k
(OPTIONAL)
NFB
SHDN
4
SHUTDOWN
3
NFB
2
GND
R2
1931 BD
(EXTERNAL)
Figure 2
U
OPERATIO
The LT1931 uses a constant frequency, current mode
control scheme to provide excellent line and load regula-
tion. Operation can be best understood by referring to the
Block Diagram in Figure 2. At the start of each oscillator
cycle, the SR latch is set, turning on the power switch Q3.
A voltage proportional to the switch current is added to a
stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator A2. When this
voltageexceedsthelevelatthenegativeinputofA2,theSR
latch is reset, turning off the power switch. The level at the
negative input of A2 is set by the error amplifier (gm) and
is simply an amplified version of the difference between
thefeedbackvoltageandthereferencevoltageof–1.255V.
In this manner, the error amplifier sets the correct peak
current level to keep the output in regulation. If the error
amplifier’s output increases, more current is taken from
the output; if it decreases, less current is taken. One
function not shown in Figure 2 is the current limit. The
switch current is constantly monitored and not allowed to
exceed the nominal value of 1.2A. If the switch current
reaches 1.2A, the SR latch is reset regardless of the state
of comparator A2. This current limit protects the power
switch as well as various external components connected
to the LT1931.
TheBlockDiagramfortheLT1931Aisidenticalexceptthat
theoscillatoris2.2MHzandresistorsR3toR6areone-half
the LT1931 values.
1931fa
4
Linear [ Linear ]
