LT1931/LT1931A
BLOCK DIAGRA
V
IN
5
–
Q1
V
OUT
R1
(EXTERNAL)
NFB
R2
(EXTERNAL)
Q2
x10
R3
30k
R4
150k
3 NFB
C
C
C
PL
(OPTIONAL)
1.2MHz
OSCILLATOR
SHDN
4
SHUTDOWN
Figure 2
OPERATIO
The LT1931 uses a constant frequency, current mode
control scheme to provide excellent line and load regula-
tion. Operation can be best understood by referring to the
Block Diagram in Figure 2. At the start of each oscillator
cycle, the SR latch is set, turning on the power switch Q3.
A voltage proportional to the switch current is added to a
stabilizing ramp and the resulting sum is fed into the
positive terminal of the PWM comparator A2. When this
voltage exceeds the level at the negative input of A2, the SR
latch is reset, turning off the power switch. The level at the
negative input of A2 is set by the error amplifier (g
m
) and
is simply an amplified version of the difference between
the feedback voltage and the reference voltage of –1.255V.
In this manner, the error amplifier sets the correct peak
current level to keep the output in regulation. If the error
amplifier’s output increases, more current is taken from
the output; if it decreases, less current is taken. One
function not shown in Figure 2 is the current limit. The
switch current is constantly monitored and not allowed to
exceed the nominal value of 1.2A. If the switch current
reaches 1.2A, the SR latch is reset regardless of the state
of comparator A2. This current limit protects the power
switch as well as various external components connected
to the LT1931.
The Block Diagram for the LT1931A is identical except that
the oscillator is 2.2MHz and resistors R3 to R6 are one-half
the LT1931 values.
4
+
R
C
RAMP
GENERATOR
Σ
–
W
V
IN
R5
80k
R6
80k
1 SW
COMPARATOR
A1
g
m
LATCH
S
DRIVER
Q
Q3
+
A2
R
+
0.01Ω
–
2 GND
1931 BD
U
1931fa
LINER [ LINEAR TECHNOLOGY ]
