LTM4600
APPLICATIONS INFORMATION
The typical LTM4600 application circuit is shown in Figure
18. External component selection is primarily determined
by the maximum load current and output voltage.
Output Voltage Programming and Margining
The PWM controller of the LTM4600 has an internal
0.6V±1% reference voltage. As shown in the block dia-
gram, a 100k/0.5% internal feedback resistor connects
V
OUT
and V
OSET
pins. Adding a resistor R
SET
from V
OSET
pin to SGND pin programs the output voltage:
V
O
=
0.6V •
100k
+
R
SET
R
SET
down when Q
DOWN
is on and Q
UP
is off. If the output
voltage V
O
needs to be margined up/down by ±M%, the
resistor values of R
UP
and R
DOWN
can be calculated from
the following equations:
(R
SET
R
UP
) • V
O
• (1+ M%)
(R
SET
R
UP
)
+
100k
=
0.6V
R
SET
• V
O
• (1– M%)
=
0.6V
R
SET
+
(100k R
DOWN
)
Input Capacitors
The LTM4600 μModule should be connected to a low
ac-impedance DC source. High frequency, low ESR input
capacitors are required to be placed adjacent to the mod-
ule. In Figure 18, the bulk input capacitor C
IN
is selected
for its ability to handle the large RMS current into the
converter. For a buck converter, the switching duty-cycle
can be estimated as:
D
=
V
O
V
IN
Table 1 shows the standard values of 1% R
SET
resistor
for typical output voltages:
Table 1.
R
SET
(kΩ)
V
O
(V)
Open
0.6
100
1.2
66.5
1.5
49.9
1.8
43.2
2
31.6
2.5
22.1
3.3
13.7
5
Voltage margining is the dynamic adjustment of the output
voltage to its worst case operating range in production
testing to stress the load circuitry, verify control/protec-
tion functionality of the board and improve the system
reliability. Figure 2 shows how to implement margining
function with the LTM4600. In addition to the feedback
resistor R
SET
, several external components are added.
Turn off both transistor Q
UP
and Q
DOWN
to disable the
margining. When Q
UP
is on and Q
DOWN
is off, the output
voltage is margined up. The output voltage is margined
LTM4600
V
OUT
R
DOWN
100k
Q
DOWN
V
OSET
PGND
SGND
R
SET
2N7002
R
UP
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
I
CIN(RMS)
=
I
O(MAX)
%
• D • (1 D)
In the above equation,
η%
is the estimated efficiency of
the power module. C1 can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitors. Note the capacitor ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
In Figure 18, the input capacitors are used as high fre-
quency input decoupling capacitors. In a typical 10A
output application, 1-2 pieces of very low ESR X5R or
X7R, 10μF ceramic capacitors are recommended. This
decoupling capacitor should be placed directly adjacent
4600fc
Q
UP
2N7002
4600 F02
Figure 2. LTM4600 Margining Implementation
9
LINER [ LINEAR TECHNOLOGY ]
