LTM4641
PIN FUNCTIONS
CROWBAR (B9): Crowbar Output Pin. Normally logic low,
with moderate pull-down strength to SGND.
If no latchoff faults are present when LATCH transitions
fromlogiclowtologichigh, theLTM4641immediatelyun-
latches. If any latchoff fault is present when LATCH is logic
high, a timeout delay timing requirement is imposed: the
LTM4641willnotunlatchuntilalllatchofffault-monitoring
pins meet operationally valid states for the full duration
of the timeout delay. If LATCH becomes logic low before
that timeout delay has expired, the LTM4641 remains
latched off and the timeout delay is reset. Unlatching the
LTM4641 can be reattempted by pulling LATCH logic high
at a later time.
When an output overvoltage (OOV) condition is detected,
theLTM4641’sfastOOVcomparatorpullsCROWBARlogic
high through a series-connected internal diode. If utilizing
LTM4641’s OOV feature, CROWBAR should connect to
the gate of a logic-level N-channel MOSFET configured to
crowbar the module’s output voltage (MCB, in Figure 1).
Furthermore, the LTM4641 latches off its output when
CROWBAR nominally exceeds 1.5V and latches HYST
logic low (see HYST).
The following are latchoff fault conditions:
•ꢀ CROWBARꢀactivatesꢀ(seeꢀCROWBAR)
•ꢀ Inputꢀlatchoffꢀovervoltageꢀfaultꢀ(seeꢀOVLO)
If not using the OOV protection features of the LTM4641,
leave CROWBAR electrically open circuit.
OV
(B10):OutputOvervoltageThresholdProgramming
PGꢁ
Pin. The voltage on this pin sets the trip threshold for the
inverting input pin of LTM4641’s fast OOV comparator.
When left electrically open circuit, resistors internal to the
•ꢀ Latchoffꢀovertemperatureꢀfaultꢀ(whenꢀOTBHꢀisꢀlogicꢀ
low; see TEMP and OTBH)
LATCHisahighimpedanceinputandmustnotbeleftelec-
trically open circuit. LATCH can be driven by a μController
in intelligent systems: a reasonable implementation for
unlatching the LTM4641 is to pull LATCH logic high for
themaximumanticipatedtimeoutdelaytime—afterwhich,
HYST can be observed to indicate whether the LTM4641
has become unlatched.
LTM4641nominallybiasOV
to666mV(OV )—11%
PGM
PTH
above the nominal V feedback voltage (600mV) that the
FB
controlloopstrivestopresenttothenoninvertinginputpin
of LTM4641’s fast OOV comparator. The aforementioned
voltages correspond proportionally to the module’s OOV
inception threshold and V ’s nominal voltage of regula-
OUT
tion, respectively. Altering the OV
voltage provides a
PGM
1V
(C6): Buffered 1V Reference Output Pin. Minimize
means to adjust the OOV threshold; its DC-bias setpoint
can be tightened with simple connections to external
components (see the Applications Information section).
Trace route lengths and widths to this sensitive analog
node should be minimized. Minimize stray capacitance to
this node unless altering the OOV threshold as described
in the Applications Information section and Appendix F.
REF
capacitance on this pin, to assure the OV
and TEMP
PGM
pinsareoperationalinatimelymanneratpower-up. 1V
REF
should never be externally loaded except as explained in
the Applications Information section.
V
(C9-C12; D9-D12; E9-E12): Power Output Pins of
OUT
the LTM4641 DC/DC Converter Power Stage. All V
pins
OUT
are electrically connected to each other, internally. Apply
output load between these pins and the GND pins. It is
recommended to place output decoupling capacitance
directly between these pins and the GND pins. Review
Table 9. See the Layout Checklist/Example section of the
Applications Information section.
LATCH (C5): Latchoff Reset Pin. When a latchoff fault oc-
curs, the LTM4641 turns off its output and latches M
HYST
on to indicate a fault condition has occurred (see HYST). To
configure the LTM4641 for latched off response to latchoff
faults, connect LATCH to SGND. As long as LATCH is logic
low, the LTM4641 will not unlatch. Regulation can be re-
+
+
sumed by cycling V or by toggling LATCH from logic low
INL
V
(D1): V
Readback Pin. This pin connects to
ORB
V
OSNS
+
to high. It is also permissible to connect LATCH to INTV ;
CC
internaltotheµModuleregulator.Itisrecommended
OSNS
–
this configures the LTM4641 for autonomous restart with a
to route this pin (differentially with V
) to a test point
ORB
timeout delay (programmed by C —see TMR).
TMR
so as to allow the user a way to confirm the integrity of
4641f
11
Linear [ Linear ]
