LTC3412
U
W
U U
APPLICATIO S I FOR ATIO
thepowerissuppliedbyawalladapterthroughlongwires,
a load step at the output can induce ringing at the input,
VIN. At best, this ringing can couple to the output and be
mistaken as loop instability. At worst, a sudden inrush of
current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
current to remain equal to IBURST regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the ITH pin will decrease. When the ITH voltage drops to
150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
IBURST is determined by the desired amount of output
voltage ripple. As the value of IBURST increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, VBURST, can be set by a
resistordividerfromtheVFB pintotheSGNDpinasshown
in Figure 1.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
R2
R1
⎛
⎝
⎞
⎟
⎠
VOUT = 0.8V 1+
⎜
The resistive divider allows the VFB pin to sense a fraction
of the output voltage as shown in Figure 2.
Pulse skipping, which is a compromise between low out-
put voltage ripple and efficiency, can be implemented by
connectingtheSYNC/MODEpintoground.ThissetsIBURST
to0A. Inthiscondition, thepeakinductorcurrentislimited
by the minimum on-time of the current comparator, and
the lowest output voltage ripple is achieved while still op-
erating discontinuously. During very light output loads,
pulse skipping allows only a few switching cycles to be
skippedwhilemaintainingtheoutputvoltageinregulation.
V
OUT
R2
V
FB
R1
LTC3412
SGND
3412 F02
Figure 2. Setting the Output Voltage
Frequency Synchronization
Burst Clamp Programming
The LTC3412’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
externalfrequencysource.Thesynchronizationfrequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set by
the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external fre-
quency should be set 25% higher than the frequency set
by the external resistor to ensure that adequate slope
compensation is present.
IfthevoltageontheSYNC/MODEpinislessthanVIN by1V,
Burst Mode operation is enabled. During Burst Mode
operation, the voltage on the SYNC/MODE pin determines
the burst clamp level which sets the minimum peak
inductor current, IBURST, for each switching cycle accord-
ing to the following equation:
3.75A
0.8V
⎛
⎜
⎝
⎞
⎟
⎠
IBURST = V
− 0.2V
(
)
BURST
VBURST is the voltage on the SYNC/MODE pin. IBURST can
be programmed in the range of 0A to 3.75A. For values of
Soft-Start
V
BURST greater than 1V, IBURST is set at 3.75A. For values
of VBURST less than 0.2V, IBURST is set at 0A. As the output
load current drops, the peak inductor current decreases to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than IBURST, the burst clamp will force the peak inductor
The RUN/SS pin provides a means to shut down the
LTC3412 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3412 in a low
quiescent current shutdown state (IQ < 1μA).
3412fb
11
Linear [ Linear ]
