LT1765/LT1765-1.8/LT1765-2.5/
LT1765-3.3/LT1765-5
APPLICATIONS INFORMATION
An internal comparator will force the part into shutdown
threshold with a duty cycle between 20% and 80%. The
input can be driven directly from a logic level output. The
synchronizing range is equal to initial operating frequency
up to 2MHz. This means that minimum practical sync
frequency is equal to the worst-case high self-oscillating
frequency (1.6MHz), not the typical operating frequency
of 1.25MHz. Caution should be used when synchronizing
above 1.8MHz because at higher sync frequencies the
amplitude of the internal slope compensation used to
prevent subharmonic switching is reduced. This type of
subharmonic switching only occurs at input voltages less
than twice output voltage. Higher inductor values will tend
to eliminate this problem. See Frequency Compensation
section for a discussion of an entirely different cause of
subharmonic switching before assuming that the cause is
insufficient slope compensation. Application Note 19 has
more details on the theory of slope compensation.
below the minimum V of 2.6V. This feature can be used
IN
to prevent excessive discharge of battery-operated sys-
tems. If an adjustable UVLO threshold is required, the
shutdown pin can be used. The threshold voltage of the
shutdown pin comparator is 1.33V. A 3μA internal current
sourcedefaultstheopenpinconditiontobeoperating(see
Typical Performance Graphs). Current hysteresis is added
above the SHDN threshold. This can be used to set voltage
hysteresis of the UVLO using the following:
VH − VL
R1=
7μA
1.33V
R2=
V −1.33V
(
)
+3μA
H
R1
V – Turn-on threshold
H
LAYOUT CONSIDERATIONS
V – Turn-off threshold
L
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For maximum
efficiency, switch rise and fall times are typically in the
nanosecond range. To prevent noise both radiated and
conducted, the high speed switching current path, shown
in Figure 5, must be kept as short as possible. Shortening
this path will also reduce the parasitic trace inductance
of approximately 25nH/inch. At switch off, this parasitic
inductance produces a flyback spike across the LT1765
switch. When operating at higher currents and input volt-
ages, with poor layout, this spike can generate voltages
across the LT1765 that may exceed its absolute maximum
Example:switchingshouldnotstartuntiltheinputisabove
4.75V and is to stop if the input falls below 3.75V.
V = 4.75V
H
V = 3.75V
L
4.75V − 3.75V
R1=
= 143k
7μA
1.33V
R2 =
= 49.4k
4.75V − 1.33V
(
)
+ 3μA
143k
Keep the connections from the resistors to the SHDN
pin short and make sure that the interplane or surface
capacitance to the switching nodes are minimized. If high
resistorvaluesareused,theSHDNpinshouldbebypassed
with a 1nF capacitor to prevent coupling problems from
the switch node.
LT1765
L1
V
IN
SW
5V
HIGH
FREQUENCY
CIRCULATING
PATH
C3
D1 C1
V
IN
LOAD
SYNCHRONIZATION
The SYNC pin is used to synchronize the internal oscilla-
tor to an external signal. The SYNC input must pass from
a logic level low, through the maximum synchronization
1765 F05
Figure 5. High Speed Switching Path
1765fd
11
Linear [ Linear ]
